An Efficient VLSI Architecture Design of Antilogarithm Converter with 10-Regions Error Correction Scheme

Abstract

An applications of signal processing are frequently used everywhere in day-to-day life. “Digital Signal Processing (DSP)” has been basic requirement of efficient and accurate arithmetic operations for performing fast and accurate signal processing. Logarithm arithmetic provides an option of that desire. In this work, it is presented an efficient VLSI implementation of an antilogarithm converter by using 10-region error correction. It provides error efficient implementation with significant hardware gain. VLSI implementation of reported and proposed antilogarithmic converters design created in Xilinx ISE 12.1. Antilogarithmic converters (reported and proposed design) are synthesized by using Synopsys design software perform the RTL Synthesis analysis by using package design compiler. This paper presents 10- region converter which considers design trade-off where proposed demonstrates 19.75%, 31.02%, 12.65%, 44.65% and 29.91% respective reduction in comparison of previous design. Error analysis was done using MATLAB for proposed conversion method and reported methods. Suggested antilogarithmic converters have 1.559% error only in comparison of 1.7327% error reported by Kuo et al. On behalf of hardware complexity and error analysis results, it can say that the proposed converters could perform better in comparisons of all aspects of reported design.