A low-voltage high-speed electronic switch based on piezoelectric transduction

Abstract

We propose a novel digital switch, the piezoelectronic transistor or PET. Based on properties of known materials, we predict that a nanometer-scale PET can operate at low voltages and relatively high speeds, exceeding the capabilities of any conventional field effect transistor (FET). Depending on the degree to which these attributes can be simultaneously achieved, the device has a broad array of potential applications in digital logic. The PET is a 3-terminal switch in which a gate voltage is applied to a piezoelectric (PE), resulting in expansion compressing a piezoresistive (PR) material comprising the channel, which then undergoes a continuous, reversible insulator-metal transition. The channel becomes conducting in response to the gate voltage. A high piezoelectric coefficient PE, e.g., a relaxor piezoelectric, leads to low voltage operation. Suitable channel materials manifesting a pressure-induced metal-insulator transition can be found amongst rare earth chalcogenides, transition metal oxides, and among others. Mechanical requirements include a high PE/PR area ratio to step up pressure, a rigid surround material to constrain the PE and PR external boundaries normal to the strain axis, and a void space to enable free motion of the component side walls. Using static mechanical modeling and dynamic electro-acoustic simulations, we optimize device structure and materials and predict performance.

Simultaneous dynamic electrical and structural measurements of functional materials

“…9), which links together strain at several lengths scales from nm (interferometry) to fm (diffraction) as well as time scales from 0.01 Hz to presently 55 Hz, allows new insights to be gleaned on the correlation between induced strain and material properties-information of crucial importance for the development of novel devices such as IBM's patented piezoelectric effect transistor. 17,30 Since the origin of the extraordinarily large electromechanical coupling and piezoelectric coefficients within 0.68PMN-0.32PT at the morphotropic phase boundary is not yet adequately explained in the literature, the ability to tune the piezoelectric response through domain engineering (with different orientations of crystal cuts, poling and/or direction of working electrodes) offers a variety of geometries that may be investigated within the novel experimental development on the XMaS beamline. The incident angle and the energy tunability that a synchrotron beamline offers allow the investigation of samples as function of x-ray penetration depth together with elemental sensitivity/selectivity.…”

Tailoring strain in microelectronic devices

“…A similar concept is the piezoelectronic transistor [16]. This device combines a piezoelectric layer and a piezoresistive material to obtain a transistor.…”

“…Recently the piezoelectronic transistor has been proposed [16]. In this device a piezoelectric layer compresses a strongly piezoresistive resistor and thus modulates the resistance.…”

“…Simulations [16] showed the possibility of increasing the applied stress by increasing the relative volume of the piezoelectric compared to the semiconductor. This solution comes at a significant price.…”

“…To obtain a larger amount of strain in the semiconductor a piezoelectric layer with a larger surface area [16] than the fin may be used. In our design this corresponds to a piezoelectric layer that is higher and longer than the FinFET itself.…”