A low-voltage 5.1-5.8-GHz image-reject downconverter RF IC

Abstract

This paper describes a single-chip implementation of a low-voltage image-reject downconverter for a 5.1-5.8-GHz radio receiver. It consists of a low-noise preamplifier (LNA) that is simultaneously noise and power matched to the RF source, and dual doubly balanced mixers coupled to the LNA by a monolithic trifilar transformer. The image-reject architecture eliminates an RF filter, thereby simplifying packaging requirements. The downconverter realizes over 36 dB of image rejection while dissipating 24 mW from a 0.9-V supply, or 18.5 mW at 1.8 V. Conversion gain is 14 dB, IIP3= 5.5 dBm, and noise figure is 6.8 dB (single sideband 50 ) when operating from a 0.9-V supply.Index Terms-Image-reject mixing, low noise amplifier, monolithic transformer, radio frequency integrated circuits, simultaneous noise/power matching, wireless receiver.

SiGe Radio Frequency ICs for Low-Power Portable Communication

“…Under certain conditions, the minimum noise figure and the maximum power transfer at the input can be achieved simultaneously, making this approach very attractive [13]. However, the amount of feedback which can be applied to the amplifier is limited by the constraints of gain and power consumption, and in most cases only a small amount of feedback can be applied [14]. Nevertheless, this technique is very useful when optimizing the performance of any LNA or mixer input stage.…”

“…Differential drive improves the -factor of the trifilar transformer and emitter degeneration inductor by approximately 50% [6]. The impedance match at the RF input realizes both minimum noise figure and maximum power transfer by employing both series feedback from the emitter via inductor and shunt feedback via the collector-base (i.e., Miller) capacitance [14].…”

A 2 V 5.1-5.8 GHz image-reject receiver with wide dynamic range

“…Parasitics for the 32-pin package were accounted for in the design. The topology used for the RF section is similar to that described in [5], [6], however, there are significant differences in this design. First, a new fully monolithic interstage coupling transformer with a noninteger turns ratio is designed to increase the overall preamplifier gain and improve coupling efficiency.…”

“…In the 5-6-GHz band, the gain available in the RF front-end is restricted by limitations of the 25-GHz technology used for this implementation [4]. The on-chip interstage coupling transformer improves the efficiency of the RF circuits (i.e., dynamic range for a given supply voltage/bias current in the LNA and mixer) through resonant parasitic absorption, and allows operation at supply voltages as low as 0.9 V. This topology has been described previously in [5] and [6]. A standard 32-pin quad flatpack (QFP) was selected to package the IC to reduce costs at the expense of larger parasitics at 5-6 GHz (e.g., lead and bondwire inductances).…”

“…Also, the preamplifier is designed so that an impedance match at the RF input realizes both minimum noise figure and maximum power transfer for the stage for the load impedance seen at the transformer primary. A simultaneous matching procedure employing both series feedback from the emitter via inductor Lee and shunt feedback via the collector-base (i.e., Miller) capacitance is used [6]. An emitter area of m was selected after careful optimization including all parasitic effects.…”