A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems

Nam, Byeong-Gyu; Kim, Hye-Jung; Yoo, Hoi‐Jun

doi:10.1109/cicc.2006.320921

Cited by 12 publications

(14 citation statements)

References 16 publications

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“…In [7]- [11], some methods were proposed with the number of segments of 2, 4 and 6 in which the parameters and coefficients of each linear segment are selected by the "trial and error" method. B.-G. Nam et al [5] presented a method of dividing the input range into 24 regions for the logarithmic and 16 regions for the anti-logarithmic approximation. In [12], the authors also presented an optimizing method for the integer binary number to logarithmic conversion.…”

Section: Existing and Proposed Methods For The Fundamental Functimentioning

confidence: 99%

“…However, these methods should be improved when they are employed for the high accuracy applications. Increasing the number of segments [5], [12] or using higher order approximation [13] The 2013 International Conference on Advanced Technologies for Communications (ATC '13) can improve the accuracy but also result in higher hardware complexity. Moreover, the multipartite table method (MTM) for approximating the elementary functions including logarithm and anti-logarithm was presented in [14] in which only tables and adders are used.…”

Section: Existing and Proposed Methods For The Fundamental Functimentioning

confidence: 99%

“…In references [5], [7]- [12], some piecewise shift-add linear approximation methods with different numbers of segments and different forms of linear difference functions were presented. In [7]- [11], some methods were proposed with the number of segments of 2, 4 and 6 in which the parameters and coefficients of each linear segment are selected by the "trial and error" method.…”

Section: Existing and Proposed Methods For The Fundamental Functimentioning

confidence: 99%

“…Moreover, the linear binary to logarithm converter and logarithm to linear binary converter are essential components in logarithmic number system (LNS) and hybrid number system (HNS) processors [5]. Hence, reducing the hardware complexity of these components can lead to a great impact on the overall HNS-DSP systems.…”

Section: Introductionmentioning

confidence: 99%

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An efficient ASIC implementation of logarithm approximation for HDR image processing

Hoang

Pham

2013

2013 International Conference on Advanced Technologies for Communications (ATC 2013)

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This paper presents an efficient ASIC implementation for the hardware approximation of the logarithm function which can be used for emerging high dynamic range image processing applications. By employing a new logarithm approximation method, the modified barrel shifter circuit and optimized leading one detector and encoder, the proposed approach can reduce the hardware area and improve the logarithm computation speed significantly while achieve the similar accuracy compared with other methods. The implementation results in 0.18-μm CMOS technology are also presented and discussed.

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Section: Existing and Proposed Methods For The Fundamental Functimentioning

confidence: 99%

Section: Existing and Proposed Methods For The Fundamental Functimentioning

confidence: 99%

Section: Existing and Proposed Methods For The Fundamental Functimentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An efficient ASIC implementation of logarithm approximation for HDR image processing

Hoang

Pham

2013

2013 International Conference on Advanced Technologies for Communications (ATC 2013)

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“…In recent years, there has been increased interest in employing logarithmic number systems (LNS) for multimedia applications in handheld devices [1][2]. Logarithmic arithmetic modules also have advantages over computational modules in linear and fixed-point systems in terms of area, delay and power dissipations.…”

Section: Introductionmentioning

confidence: 99%

Design of a Logarithmic Domain 2-D Convolver for Low Power Video Processing Applications

Ngo

Asari

2009

2009 Sixth International Conference on Information Technology: New Generations

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In this paper, a design and implementation of an efficient, low power log-based 2-D convolution unit (convolver) for video processing applications is proposed. The design of the proposed convolver utilizes approximation method with error correction technique to transform data to logarithmic domain for reduced power consumption. A novel design and implementation of a modular approach for leading bit detection module that is used to compute the binary logarithm is presented. A partitioning and gating technique is also presented to reduce the switching activities based on detection of insignificant data bits. It is observed that the proposed logarithmic-domain multiplier reduces power consumption in two common image filtering operations by more than 50% compared to conventional linear-domain 2D convolvers.

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Mobile 3D Graphics

Yoo

Woo

Sohn³

et al. 2010

Mobile 3D Graphics SoC

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A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems

Cited by 12 publications

References 16 publications

An efficient ASIC implementation of logarithm approximation for HDR image processing

An efficient ASIC implementation of logarithm approximation for HDR image processing

Design of a Logarithmic Domain 2-D Convolver for Low Power Video Processing Applications

Mobile 3D Graphics

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