A low power tunable Gm–C filter based on double CMOS inverters in 0.35 μm

Abstract

In this article, an inverter based transconductor using double CMOS pair is proposed for implementation of a second order lowpass G m -C Filter. The proposed operational transconductance amplifier (OTA) and biquad filter are designed using standard 0.35 lm CMOS technology. Simulation results demonstrate the central frequency tunability from 10 kHz to 2.8 MHz which is suitable for the wireless specifications of Bluetooth (650 kHz), CDMA 2000 (700 kHz) and Wideband CDMA (2.2 MHz) applications. The power consumption of the filter is 445 nW and 178 lW at 10 kHz and 2.8 MHz from 3.3 V supply voltage, respectively. The active area occupied by the designed filter on the silicon is 215 9 720 lm 2 . The proposed approach guarantees the upper bound on THD to be -40 dB for 300 mVpp signal swing. Employing the double CMOS pair in the inverters causes PSRR to reach 68.6 dB which is higher than similar works.

Inverter‐based, low‐power and low‐voltage, new mixed‐mode Gm‐C filter in subthreshold CNTFET technology

“…However, the inverters are generally used in digital applications, but they can also be used as operational transconductance amplifier (OTA) blocks in some analogue applications which require low chip area as well as LP consumption. These applications are discussed in the previously published literature, such as filter circuits [20][21][22][23][24][25]. However, as it is discussed in [20], a low-pass Gm-C filter based on the Nauta's trans-conductance circuit consisting of six CMOS inverters is presented.…”

“…However, as it is discussed in [20], a low-pass Gm-C filter based on the Nauta's trans-conductance circuit consisting of six CMOS inverters is presented. However, this filter and its extended versions [21][22][23][24][25] suffer from the lack of universality and the ability to implement mixed-mode structure, while they show a high power consumption value, that makes them unsuitable candidates for LV/LP circuit design.…”

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

“…Power consumption is reduced using inverters [13][14][15][16][17][18] instead of conventional OTAs, to design the delta-sigma ADCs. This is because an inverter with both PMOS-and NMOS-input transistors has a greater transconductance and a large slewing rate [13].…”

Projeto de um OTA Baseado em Inversores em Processo CMOS de 130 nm

“…(CC BY 4.0) | ISSN 2525-3409 | DOI: http://dx.doi.org/10.33448/rsd-v9i6.3334 3 Pirmohammadi & Zarifi, 2012;Ramasamy & Venkataramani, 2011;Vlassis, 2012;Nicholson, Iberzanov, Jenkins, Hamilton, & Lehmann, 2016).…”

“…Os autores do trabalho (Pirmohammadi & Zarifi, 2012) utilizaram a topologia CMOS de dupla entrada para construção dos inversores do OTA que resultou num filtro com maior linearidade da corrente de saída proporcional à tensão diferencial. Ramasamy em (Ramasamy & Venkataramani, 2011) utilizou a mesma topologia CMOS dupla entrada para construir um amplificador de ganho variável.…”