A Low-Power Time-Domain Comparator for IoT Applications

Hassan, Ali H.; Mostafa, Hassan; Salama, Khaled N.; Soliman, Ahmed M.

doi:10.1109/mwscas.2018.8624101

Cited by 7 publications

(3 citation statements)

References 21 publications

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“…Besides the dominant pole, the proposed op-amp has two pairs of highfrequency poles: one at V Y (V YP ) and another at V outP (V outM ). The output high-frequency pole f Pout is given in (7).…”

Section: Frequency Responsementioning

confidence: 99%

“…The use of an integrated fully differential amplifier for modern mixed-signal [3] processing applications can provide many advantages such as: (a) increased immunity to external noise, (b) suppressed noise from power supply, (c) increased output voltage swing [4,5] for a given voltage rail, which is ideal for low-voltage systems, and (d) reduced even-order harmonics. Thus, designing a power-efficient fully differential amplifier [6] that can drive a wide range of resistive and capacitive loads is very useful for today's batteryoperated portable electronic equipment, e.g., for the Internet of Things (IoT) [7] applications. The conventional class-A [8] fully differential Miller op-amp has an asymmetric slew-rate (SR) and a current efficiency CE = I outpk /I totQ < 0.5, where I outpk is the minimum of the positive and negative peak output currents: I outpk = MIN{I outpk + , I outpk − }.…”

Section: Introductionmentioning

confidence: 99%

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Fully Differential Miller Op-Amp with Enhanced Large- and Small-Signal Figures of Merit

Paul

Ramírez-Angulo

Vázquez-Leal

et al. 2022

JLPEA

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A highly power-efficient, fully differential Miller op-amp with accurately controlled output quiescent current is introduced. The op-amp can drive both capacitive and resistive load due to the presence of the auxiliary amplifier. This amplifier helps to achieve class AB operation of the proposed op-amp. The fully differential auxiliary amplifier is compact and uses a resistive local common-mode feedback network. It consumes only 6% of the total current of the op-amp. The proposed op-amp has several innovative features. Incorporating the auxiliary amplifier helps to improve the unity gain frequency, power efficiency, slew-rate, and common-mode rejection ratio of the proposed op-amp. It can drive a wide range of resistive (200 Ω–1 MΩ) and capacitive loads (5 pF–300 pF). The op-amp has a large signal dynamic current efficiency of 8.6 and a large signal static current efficiency of 7.9. The small-signal figure of merit is 8.7 for RL = 1 MΩ and 7.3 for RL = 200 Ω.

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Section: Frequency Responsementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fully Differential Miller Op-Amp with Enhanced Large- and Small-Signal Figures of Merit

Paul

Ramírez-Angulo

Vázquez-Leal

et al. 2022

JLPEA

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“…The comparator is a crucial component of ADCs and consumes a lot of power in the device. Our main objective is to develop a low-power, high-speed comparator [10][11]. Panda et al suggested an innovative lower power 64-bit CMOS binary comparator.…”

Section: Introductionmentioning

confidence: 99%

Adiabatic Logic Based Energy Efficient Architecture of 1-Bit Magnitude Comparator for IOT Applications

Sanadhya¹,

Sanadhya²

2022

Journal of Internet Technology

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<p>The Internet of Things (IoT) applies the sensors and microcontrollers and links them through the internet. The eventual objective of low-power devices for Internet of Things is to lesser the overall system power and to extend battery life. For the development of energy efficient IoT devices, novel adiabatic techniques are proposed. By improving the performance of the comparator, one can improvise the whole system performance. The efficacy of computing devices depends on the performance of arithmetic circuits, including comparator. This paper proposes 1-bit comparator design using adiabatic techniques such as DC-DB PFAL (Direct current diode-based positive feedback adiabatic logic) and MPFAL (Modify positive feedback adiabatic logic) which are well-suited with an extensive range of applications (e.g. IoT sensors and an inbuilt analog to digital converter). For performance analysis, the results are compared together along with the other adiabatic and non adiabatic designs already reported in the literature. This paper proposes a way to decrease the dissipation of power and transistor count in binary circuits as it is one of the primary concerns. From the results, it is found that the design using DC-DB PFAL logic shows an improvement in power-delay-product of 69%, 94% and 90% compared to MPFAL, PFAL and ECRL techniques respectively.</p> <p> </p>

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