A Low-Power Sigma-Delta Modulator for AI Voice Applications

Abstract

This paper presents an 18-bits discrete Sigma-Delta modulator with a bandwidth of 4 kHz. The proposed modulator targets artificial intelligence voice applications where the readout of small-bandwidth signals is required. Sigma-Delta modulator includes an noise shaping filter, one-bit quantizer, and digital-to-analog conversion (DAC). The op-amp noise shaping filter is controlled by a high-frequency clock that alternates between sampling and integration stages. An op-amp noise shaping filter sharing technique is presented to reduce the power consumption caused by several noise shaping filters. Furthermore, by multiplexing the DAC of the power supply voltage and the ground voltage, the power consumption is further lowered. The modulator is implementd in UMC 0.11μm CMOS process. Post-layout simulation results show that the signal-to-noise ratio is 104.6dB, and the power consumption is 104 μW when the power supply voltage is 1.2V and the reference voltage is 0.6V.