A low power, self-biased, bandwidth tracking semi-digital PLL design

Yogesh, Mitesh; Dietl, Markus; Sareen, Puneet; Dewan, Ketan

doi:10.1109/icedsa.2012.6507782

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“…Dynamic bandwidth control [13][14][15][16][17][18]i sa ne f ficient way to solve the conflict between signal quality and settling time. To ensure loop stability, the loop bandwidth is limited to 10% of the input reference frequency.…”

Section: Introductionmentioning

confidence: 99%

Phase‐error cancellation technique for fast‐lock phase‐locked loop

Ding

Liu

2016

IET Circuits, Devices & Systems

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This paper presents a phase-error cancellation (PEC) technique that can be employed to achieve fast lock in analogue phase-locked loops (PLLs). The PLL works in fast-lock mode during phase and frequency tracking, and is switched to normal mode after it is almost locked. Unstable system topology is introduced in this system for fast locking. This PEC technique is proposed to cancel the phase error when the output frequency approaches the target value. Due to the inherent oscillation nature of the intentionally designed unstable system in fast-lock mode, the time for PEC can be predicted based on some known parameters. A PLL is simulated in 0.13 µm CMOS process with 1.2 V supply to verify the proposed PEC technique. Simulation results prove that this technique can reduce at least 87% settling time as compared with conventional PLLs.

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