Phase‐error cancellation technique for fast‐lock phase‐locked loop

Ding, Zhaoming; Liu, Haiqi; Li, Qiang

doi:10.1049/iet-cds.2015.0201

Cited by 2 publications

(1 citation statement)

References 23 publications

(25 reference statements)

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“…The phase-frequency detector (PFD) is one of the most important electronics circuits, which plays an important role in commonly used communication circuit's design [4]. PFD is the main block in the phaselocked loops (PLLs) or delay-locked loops (DLLs) *Corresponding Author Email: m.gholami@umz.ac.ir (M. Gholami) architectures [5,6]. This circuit recognizes the phase and frequency difference between two signals by examining them.…”

Section: Introductionmentioning

confidence: 99%

Novel Phase-frequency Detector based on Quantum-dot Cellular Automata Nanotechnology

Gholami

Roshan

2020

IJE

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The electronic industry has grown vastly in recent years, and researchers are trying to minimize circuits delay, occupied area and power consumption as much as possible. In this regard, many technologies have been introduced. Quantum Cellular Automata (QCA) is one of the schemes to design nano-scale digital electronic circuits. This technology has high speed and low power consumption, and occupies very little area. Phase-locked loops (PLLs) and delay-locked loops (DLLs) are blocks that are commonly used in telecommunication applications. One of the most important parts in DLL and PLL is the phasefrequency detector. Therefore, the design of this circuit in QCA technology is of great importance. In this paper, two new phase-frequency detectors sensitive to falling and rising edge have been introduced in QCA technology. Both of the designs are composed of 104 cells; occupy only 0.13 μm 2 of an area and 1.5 QCA clock cycles latency. The designs are in one layer and all the inputs and outputs are available to be used by another circuit.

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Section: Introductionmentioning

confidence: 99%

Novel Phase-frequency Detector based on Quantum-dot Cellular Automata Nanotechnology

Gholami

Roshan

2020

IJE

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Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology

Sun,

Luo,

Deng

et al. 2024

Electronics

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This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from the phase frequency detector (PFD) in order to optimize the dead-zone effect while dynamically switching an auxiliary charge pump (CP) module to realize fast phase locking. Furthermore, a TDC-controlled three/five-stage dual-mode adaptively continuously switched VCO is proposed to optimize the phase noise (PN) and power efficiency, leading to an optimal performance tradeoff of the PLL. Based on the 180 nm/1.8 V standard CMOS technology, the complete PLL design and a corresponding simulation analysis are implemented. The results show that, with a 1 GHz reference signal as the input, the output frequency is 50–324 MHz, with a wide tuning range of 260 MHz and a low phase noise of −98.07 dBc/Hz@1 MHz. The key phase-locking time is reduced to 1.11 μs, and the power dissipation is lowered to 1.86 mW with a layout area of 66 μm × 128 μm. A significantly remarkable multiobjective performance tradeoff with topology optimization is realized, which is in contrast to several similar design cases of PLLs.

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Phase‐error cancellation technique for fast‐lock phase‐locked loop

Cited by 2 publications

References 23 publications

Novel Phase-frequency Detector based on Quantum-dot Cellular Automata Nanotechnology

Novel Phase-frequency Detector based on Quantum-dot Cellular Automata Nanotechnology

Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology

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