A low-power reconfigurable analog-to-digital converter

Abstract

This thesis presents the concept, theory and design of a low power CMOS analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption. The converter achieves the wide operating range by reconfiguring (1) its architecture between pipeline and delta-sigma modes (2) by varying its circuit parameters such as size of capacitors, length of pipeline, oversampling ratio, among others and (3) by varying the bias currents of the opamps in proportion with converter sampling frequency, accomplished through the use of a phase-locked loop. Target input signals for this ADC include high frequency and moderate resolution signals such as video and low I.F. in radio Receivers, low frequency and high resolution signals from seismic sensors and MEMs devices, and others that fall in between these extremes such as audio, voice and general purpose data-acquisition. This converter also incorporates several power reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design.At a converter power supply at 3.3V, the converter achieves a bandwidth range of 0-10MHz over a resolution range of 6 -16 bits, and parameter reconfiguration time of 12 clock cycles. Its PLL lock range is measured at 20KHz to 40MHz. In the delta-sigma mode, it achieves a maximum SNR of 94dB and second and third harmonic distortions of 102dB and 95dB, respectively at 10MHz clock frequency, 9.4KHz bandwidth, and 17.6mW power. In the pipeline mode, it achieves a maximum DNL and INL of +/-0.55LSBs and +/-0. 82LSBs, respectively, at 11-bits of resolution, at a clock frequency of 2.6MHz and 1MHz tone with 24.6mW of power.

Signal processing and analog/RF circuit design: cross-discipline interactions and technical challenges

“…Ideally, this noise term approaches zero as more samples are averaged. Once (1 + ε)V C AL is obtained, Similar concept has been used to estimate the offset error [33], as shown in Fig. 19(b).…”

Adaptive quantization using piecewise companding and scaling for Gaussian mixture

“…With the proliferation of autonomous sensors, and digital devices, there has been an increasing demand for reconfigurable analog-to-digital converters (ADC) [12], where the proposed adaptive quantizer can have important applications.…”

A low-power reconfigurable analog-to-digital converter

“…While it is possible to execute a calibration run for a given process and chip, calibration adds significant cost. This work proposes the idea of a single converter [20][21] that can morph itself into different topologies to cover the desired continuum of resolution and bandwidth space with minimum power at each performance level. The proposed converter is designed to provide a significantly larger reconfigurability space.…”