A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme

Yang, Byung‐Do; Lee, Jae-Eun; Kim, Jang-Su; Cho, Junghyun; Lee, Seung-Yun; Yu, Byoung–Gon

doi:10.1109/iscas.2007.377981

Cited by 213 publications

(123 citation statements)

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“…To do this, they use a dirty bit within each cache line that retains whether the cache line is modified or not. Yang et al present the data comparison write that compares each bit in a PCM page and then writes only modified bits [6]. Similar work is also performed by Zhou et al [5].…”

Section: Related Workmentioning

confidence: 94%

LDF-CLOCK: The Least-Dirty-First CLOCK Replacement Policy for PCM-based Swap Devices

Yoo¹,

Lee²,

Bahn³

2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

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Section: Related Workmentioning

confidence: 94%

LDF-CLOCK: The Least-Dirty-First CLOCK Replacement Policy for PCM-based Swap Devices

Yoo¹,

Lee²,

Bahn³

2015

JSTS:Journal of Semiconductor Technology and Science

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“…Considering the distinguished properties of PCM, some hardware optimizations have already been proposed, e. g., data comparison writes [14] or partial writes [7], to reduce the number of bits written to PCM. These hardware optimizations would be integrated into the conventional memory controller or even implemented in a dedicated memory controller for PCM.…”

Section: Wear-aware Buffer Managementmentioning

confidence: 99%

Wear-Aware Algorithms for PCM-Based Database Buffer Pools

Chen

et al. 2014

Web-Age Information Management

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Abstract. PCM can be used to overcome the capacity limit and energy issues of conventional DRAM-based main memory. This paper explores how the database buffer manager can deal with the write endurance problem, which is unique to PCM-based buffer pools and not considered by conventional buffer algorithms. We introduce a range of novel buffer algorithms addressing this problem, called wear-aware buffer algorithms, and study their behavior using trace-driven simulations.

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“…These techniques have largely focused on hardware mechanisms. Yang et al [27] and Zhou et al [8] use datacomparison write to reduce bit programming. By comparing each bit in the read buffer with the new data bit, the corresponding memory bit is only programmed if the new data bit differs from the old bit.…”

Section: Related Workmentioning

confidence: 99%

Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory

Bock

Childers

Melhem

et al. 2011

(Ieee Ispass) Ieee International Symposium on Performance Analysis of Systems and Software

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Abstract-Phase Change Memory (PCM) is an emerging technology that has been recently considered as a cost-effective and energy-efficient alternative to traditional DRAM main memory. Due to the high energy consumption of writes and limited number of write cycles, reducing the number of writes to PCM can result in considerable energy savings and endurance improvement. In this paper, we introduce the concept of useless write-backs, which occur when a dirty cache line that belongs to a dead memory region is evicted from the cache (a dead region is a memory location that is not used again by a program). Since the evicted data is not used again, the write-back can be safely avoided to improve endurance and energy consumption.This paper presents a limit study on the improvement that passing information to the memory system about useless writebacks has on the endurance and energy consumption of systems based on PCM main memory. We developed algorithms to measure the number of useless write-backs to PCM for three different types of memory regions and we present an energy model to determine the maximum energy savings that could potentially be achieved through such a scheme. Our results show that avoiding useless write-backs can save up to 19.8% of energy and improve endurance by up to 26.2%.

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A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme

Cited by 213 publications

References 1 publication

LDF-CLOCK: The Least-Dirty-First CLOCK Replacement Policy for PCM-based Swap Devices

LDF-CLOCK: The Least-Dirty-First CLOCK Replacement Policy for PCM-based Swap Devices

Wear-Aware Algorithms for PCM-Based Database Buffer Pools

Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory

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