Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory

Bock, Santiago; Childers, Bruce R.; Melhem, Rami; Mossé, Daniel; Zhang, Youtao

doi:10.1109/ispass.2011.5762715

Cited by 22 publications

(11 citation statements)

References 32 publications

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“…We are especially interested in this class of squashed stores. For languages with explicit deallocation, the free or delete instructions can be forwarded to the cache so that the associated cached locations can be marked non-dirty [8,16,21]. Subsequent eviction would then refrain from writing those values to main memory.…”

Section: Background and Related Workmentioning

confidence: 99%

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Recycling trash in cache

Shidal

Spilo

Scheid

et al. 2015

Proceedings of the 2015 International Symposium on Memory Management

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The disparity between processing and storage speeds can be bridged in part by reducing the traffic into and out of the slower memory components. Some recent studies reduce such traffic by determining dead data in cache, showing that a significant fraction of writes can be squashed before they make the trip toward slower memory. In this paper, we examine a technique for eliminating traffic in the other direction, specifically the traffic induced by dynamic storage allocation. We consider recycling dead storage in cache to satisfy a program's storage-allocation requests.We first evaluate the potential for recycling under favorable circumstances, where the associated logic can run at full speed with no impact on the cache's normal behavior. We then consider a more practical implementation, in which the associated logic executes independently from the cache's critical path. Here, the cache's performance is unfettered by recycling, but the operations necessary to determine dead storage and recycle such storage execute as time is available. Finally, we present the design and analysis of a hardware implementation that scales well with cache size without sacrificing too much performance.

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Section: Background and Related Workmentioning

confidence: 99%

“…Such data, even if marked dirty, need not be written on eviction. For languages with explicit deallocation, the death of data in cache is indicated directly by the application, and the stores associated with such data can also be squashed [8].…”

Section: Introductionmentioning

confidence: 99%

Recycling trash in cache

Shidal

Spilo

Scheid

et al. 2015

Proceedings of the 2015 International Symposium on Memory Management

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“…The caches write the page number into the PIN registers and set the PIN valid bits. If the destination page is a PCM address, the MM 3 With the usual cache indexing function. tells the caches to flush the source physical page (step 1.b).…”

Section: Concurrent Page Migrationmentioning

confidence: 99%

“…Other studies have focused on PCM in embedded systems [9,13,16]. Numerous papers have studied architectural techniques for improving performance, energy consumption and endurance of PCMbased memory systems [20,21,10,4,3,8].…”

Section: Related Workmentioning

confidence: 99%

Concurrent page migration for mobile systems with OS-managed hybrid memory

Bock

Childers

Melhem

et al. 2014

Proceedings of the 11th ACM Conference on Computing Frontiers

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Mobile systems are executing applications with increasingly large memory footprints on more processor cores. New execution paradigms for quickly suspending and resuming an application have also become common. Energy consumption remains a paramount concern. Consequently, phase-change memory (PCM) has been suggested for main memory to increase capacity, provide non-volatility for suspend/resume and decrease energy consumption. Because it has limitations for writes, a large PCM is often used along with a small DRAM for good performance. The two memory types may be managed by the operating system, which selects where to allocate pages and schedules background migrations between memory types to move data. To ensure correctness, an application that writes to a migrating page must be paused until the migration completes. Because PCM has long write latency, this situation happens frequently in hybrid memory, leading to long pauses that hurt application responsiveness and performance. This paper describes concurrent page migration (CPM) to alleviate the pauses by buffering writes to migrating pages through the last-level cache. CPM improves performance by up to 22% for single-programmed workloads (17% average) and 13% for multi-programmed workloads (8% average). The technique also preserves the energy and non-volatility benefits of hybrid main memory.

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“…[16] introduced techniques to reduce useless write-backs to avoid dead data write back from cache. [17] proposed a content-aware block replacement algorithm that finds the free block with similar content to reduce write.…”

Section: Related Workmentioning

confidence: 99%

A Software-hardware Collaborating Framework for Wear Leveling on Phase Change Memory

Chen

Wu³

2012

2012 IEEE 14th International Conference on High Performance Computing and Communication &Amp; 2012 IEEE 9th International Confe

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DRAM has been used as main memory in most systems, but its scalability and energy consumption are difficult to improve because of its architecture nature. Phase change memory (PCM) is a new non-volatile memory, which addresses these problems and is a promising candidate to replace DRAM as main memory. Since PCM cell has a very limited lifetime, many hardware methods have been proposed to improve its endurance with only low-level information about physical memory operations. Meanwhile, operating system manages physical page mapping, and it has the knowledge of memory layout as well as memory requirements of each process. This paper investigates write behaviors of different memory areas of processes, and proposes a software-hardware collaborating framework that captures process write behavior with simple hardware to enable process write behavior predication by operating system. The framework combines operating system and PCM controller that exploits write behaviors of processes to aid in PCM wear leveling. The results show this framework helps reduce PCM page swaps for wear leveling by 63% on average. And it also lowers the writes of the most worn page by 12% with single process, and by 21% with two parallel processes sharing the PCM.

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Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory

Cited by 22 publications

References 32 publications

Recycling trash in cache

Recycling trash in cache

Concurrent page migration for mobile systems with OS-managed hybrid memory

A Software-hardware Collaborating Framework for Wear Leveling on Phase Change Memory

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