A low-power phase change memory based hybrid cache architecture

Mangalagiri, Prasanth; Sarpatwari, K.; Yanamandra, Aditya; Narayanan, Vijaykrishnan; Xie, Yuan; Irwin, M.J.; Karim, Osama Awadel

doi:10.1145/1366110.1366204

Cited by 51 publications

(16 citation statements)

References 7 publications

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“…Our in-house DRAM simulator is based on DRAMsim [7,15] and follows standard JEDEC protocols for DDR3 memory [19]. From [5,9] it is clear that PCM access protocols will not be much different from those of DRAM. Therefore we extend our DRAM simulator by accounting for the fundamental differences between DRAM and PCM technologies, although following similar memory access protocols.…”

Section: Methodsmentioning

confidence: 99%

“…The PCM cell has an area ranging from 22.68 F 2 to 9.60 F 2 , but PCM is expected to have multilevel cells, which make it a high capacity memory. [5] The PCM cell area is constrained by two factors: (a) the size of chalcogenide-based phase-change materials (GSTs) and (b) the size of the selector device that could be a MOSFET, a BJT, or a diode [9].…”

Section: Pcm Technologymentioning

confidence: 99%

“…To this end, traditional DRAM memories have become less attractive as scaling becomes a problem and energy efficiency gets worse. Phase Change Memory (PCM) [5][6] [9] has gained increasing popularity as a potential solution. An important advantage afforded by PCM is its high capacity, which has proven useful in the reduction of page faults.…”

Section: Introductionmentioning

confidence: 99%

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Energy efficient Phase Change Memory based main memory for future high performance systems

Bheda

Poovey

Beu

et al. 2011

2011 International Green Computing Conference and Workshops

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Phase Change Memory (PCM) has recently attracted a lot of attention as a scalable alternative to DRAM for main memory systems. As the need for high-density memory increases, DRAM has proven to be less attractive from the point of view of scaling and energy consumption. PCM-only memories suffer from latency issues, high write energy, and the problem of limited write endurance. Research in this domain has focused mainly on using various hybrid memory configurations to address these shortcomings. A commodity DRAM module as a cache for PCM memory has emerged as a potential solution. But this method requires use of a separate memory controller and is unable to achieve better performance than a DRAM-only based memory at low energy.We propose a PCM based main memory system design using a small, embedded DRAM (eDRAM) cache to replace the row buffers in the PCM memory chip. This reduces the high latencies of PCM and the energy consumption of the main memory system. Our methodology also eliminates the need for separate memory controllers. Through simulation results, we show competitive performance by reducing average memory access time of a slow PCM based memory and significant energy reductions against a DDR3 commodity DRAM memory system of similar storage size. Our proposed system is highly energy efficient and provides 35.02%improvement in EDP over a DRAM-only system. Our system consumes less energy than the state-of-the-art PCM hybrid system using a commodity DRAM cache.

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Section: Methodsmentioning

confidence: 99%

Section: Pcm Technologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Energy efficient Phase Change Memory based main memory for future high performance systems

Bheda

Poovey

Beu

et al. 2011

2011 International Green Computing Conference and Workshops

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show abstract

“…In [26], Mangalagiri et al combined both SRAM and PRAM technologies to propose a hybrid L1 instruction cache. The L1 memory is split into an SRAM-based cache and a PRAM-based cache.…”

Section: Related Workmentioning

confidence: 99%

Design of Hybrid Second-Level Caches

Valero

Sahuquillo

Petit

et al. 2015

IEEE Trans. Comput.

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“…Finally, phase change random access memory (PRAM) is being considered as a candidate for future memory technologies. Mangalagiri et al [15] investigate challenges in PRAM-based cache hierarchies. Their results show an 80% decrease in the leakage energy of a 2-level cache hierarchy.…”

Section: Article In Pressmentioning

confidence: 99%