A low power open multimedia application platform for 3G wireless

Song, J.; Shepherd, Thomas; Chau, Minh Quang; Huq, A. M. Anisul; Syed, L.; Roy, Subir Kumar; Thippana, Achuta; Shi, Kun; Ko, Uming

doi:10.1109/soc.2003.1241547

Cited by 11 publications

(7 citation statements)

References 1 publication

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“…However, by taking a closer look at Eqs. (4) and (5), T I IQ/IT , T P IQ/IT , and T P inter , and considering all the different cases of prediction modes and MB types, we can bring about significant savings in computational power of the MPU. The equations indicate that, when the MPU stays at the highest frequency (e.g., MPU_active-1), it consumes large amounts of power.…”

Section: Imprecise Model For Power-aware Video Decodingmentioning

confidence: 99%

“…Contrarily, if video decoding only needs to satisfy soft real-time constraints so that only broad estimates are required, we can simplify several subroutines in Eqs. (4) and (5) to let the MPU stay at a lower frequency to save power. We summarize these techniques in the following paragraphs.…”

Section: Imprecise Model For Power-aware Video Decodingmentioning

confidence: 99%

“…As a result of two major concerns stated above, in the recent trend for portable devices, hardware system designers [4][5][6] often integrate a RISC processor with coprocessors (DSP or ASIC) into one SoC chip. By this way, portable devices can take advantage of modern VLSI designs to achieve better cost-effective and rich functionality in more compact size.…”

Section: Introductionmentioning

confidence: 99%

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Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part II: Application Programming

Chen

Liu

Yang

et al. 2010

J Sign Process Syst

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Two representative multimedia applications-AAC and H.264/AVC decoders on the parallel architecture core (PAC) SoC are introduced in the second part of the two introductory papers. The applications have been programmed on the PACDSP core and the PAC SoC to demonstrate the high-performance, low-power DSP computations and the effectiveness of the dynamic voltage and frequency scaling (DVFS) capability on the heterogeneous multicore SoC. First, techniques to exploit data-and instruction-level parallelisms existing in the application kernels are described for performance optimizations on the clustered VLIW architecture of PACDSP with the distributed register organization. Next, two variation techniques of asymmetric programming model are introduced by examples of decoders. Then, the energy efficiency of the programmable multimedia SoC is demonstrated using an innovative power-aware H.264/AVC decoder. Finally, a DVFS-aware framework for soft real-time video playback is provided by extending the power-aware decoding scheme. The work provides practical references of realizing multimedia applications on PAC SoC suitable for richfunction and resource constraint portable devices.

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Section: Imprecise Model For Power-aware Video Decodingmentioning

confidence: 99%

Section: Imprecise Model For Power-aware Video Decodingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part II: Application Programming

Chen

Liu

Yang

et al. 2010

J Sign Process Syst

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“…OMAP (Open Multimedia Application Platform) is a solution intended primarily for mobile wireless communications and next generation embedded devices [3,23,26]. OMAP makes use of an embedded ARM processor core and a Texas Instruments TMS320C55X DSP core.…”

Section: Multiprocessor Dsp For Mobile Applicationsmentioning

confidence: 99%

“…The ARM processor and the DSP communicate with each other through a set of mailboxes [23]. When the ARM processor, which acts as a "master," has to dispatch a task to the DSP, it writes a message in the MPU2DSP mailbox.…”

Section: Multiprocessor Dsp For Mobile Applicationsmentioning

confidence: 99%

Multiprocessor architectures for embedded system-on-chip applications

Ravikumar

17th International Conference on VLSI Design. Proceedings.

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Real-time multimedia applications that involve processing of video and audio streams demand computational performance of a few Giga operations per second, which cannot be obtained using a single processor. An embedded system intended for such an application must also support networking and IO interfaces, which are best handled by dedicated interface processors that are coordinated by a housekeeping processor. Dedicated processors may also be necessary for parsing and processing video/audio stream and, video/graphics rendering. In this paper, we provide an overview of multiprocessor architectures that are evolving for such embedded applications. We argue that the VLSI design challenges involved in designing an equivalent uniprocessor solution for the same application may make such a solution prohibitively expensive, making multiprocessor SoC an attractive alternative.

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