A Low-Power Low-Cost GFSK Demodulator With a Robust Frequency Offset Tolerance

Abstract

A low-power low-cost Gaussian frequency shift keying demodulator with a robust frequency offset tolerance is presented. A novel automatic pulse duration calibration is employed to keep the pulse durations of the zero-crossing detection output constant against process variation. Additionally, a discrete-time differentiator is adopted to eliminate the negative effect of frequency offset and drift. The demodulator is implemented in a 0.18-μm CMOS process and the area is approximately 0.08 mm 2 . It can recover data even as the intermediate frequency drifts from 1.5 up to 3.7 MHz during demodulation and requires a signal-to-noise ratio of less than 16.5 dB for a 0.1% bit error rate. The circuit consumes only a 0.51-mA current from a 1.8-V supply.Index Terms-Frequency offset tolerance, Gaussian frequency shift keying (GFSK) demodulation, low cost, low power.

Ultra‐low‐power FSK demodulator with frequency‐offset tolerance

“…First, the time lengths of the FSK‐modulated signal's periods rather than of its pulse durations are converted into voltage levels, which can effectively prevent the variation of the pulse duration affecting the demodulation performance adversely. Second, a DTD with the bandpass filtering property is adopted to restrain the fluctuation of the Directly Coupled (DC) component of the time–voltage conversion results, which is nearly unavoidable because of the carrier frequency offset and the process voltage and temperature variation from damaging or even disabling the demodulation.…”

“…For instance, the voltage of signal V C <0> is sampled by CKS<1> in the second period to form the voltage signal V SN , then it is sampled in the fifth period by CKS<4> to generate the voltage signal V SP , which makes V SN precede V SP by three periods of V IN . In other words, V SP can be considered as a delayed copy of V SN , which aims at maximizing the voltage difference between V SP and V SN even in the case of high data rate and small modulation index . Afterwards, V SP and V SN are buffered to avoid charge leakage from the capacitors in the PVC.…”

“…, in the proposed demodulator the whole periods rather than the pulse durations of signal are converted, so that it can avoid the pulse duration fluctuations that adversely affect the voltage levels after conversion. Furthermore, the discrete‐time differentiation (DTD) technology implemented in our previous design is applied in this new demodulator to eliminate the negative effect caused by the frequency offset. Since there are only a few analog components integrated into the demodulator and the whole system runs at low frequency, the total power consumption can be kept at an ultra‐low level.…”

Timing and carrier synchronization in wireless communication systems: a survey and classification of research in the last 5 years

“…Note that cyclic prefix can mainly remove the ISI and proper design of the cyclic prefix length has been a design issue under research. Table II CLASSIFICATION OF PAPERS ON TIMING OR CARRIER SYNCHRONIZATION, 2010-2014 Communication System Single-carrier Multi-carrier SISO [31], [32], [33], [34], [35], [36], [37], [38], [39], [40], [41], [42], [43], [44], [45], [46], [47], [48], [49], [50], [51], [52], [53], [54], [55], [56], [57], [58], [59], [60], [61], [62], [63], [64], [65], [66], [67], [68], [69], [70], [71], [72], [73], [74] [75], [76], [77],…”

A 88μWdigital phase-domain GFSK demodulator compatible with low-IF and zero-IF receiver with preamble detection for BLE

“…Limiter based demodulator utilizes multiple zero-crossing pulses throughout a symbol period for demodulation. For example, zero crossing detector (ZCD) generates a pulse when the clipped IF signal crosses zero level [7,8]. The generated pulse is followed by low pass filtering that results in demodulated data.…”