A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

Ritzenthaler, R.; Schram, T.; Spessot, A.; Caillat, C.; Aoulaiche, M.; Cho, Moon Ju; Noh, K. B.; Son, Yunik; Na, Hoon Joo; Kauerauf, T.; Douhard, Bastien; Nazir, Aftab; Chew, Soon Aik; Milenin, Alexey; Altamirano-Sánchez, Efraín; Schoofs, Geert; Albert, Johan; Sebai, Farid; Vecchio, E.; Paraschiv, Vasile; Vandervorst, Wilfried; Lee, Sun-Ghil; Collaert, N.; Fazan, P.; Horiguchi, N.; Thean, Aaron

doi:10.1109/ted.2014.2331371

Cited by 21 publications

(7 citation statements)

References 27 publications

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“…6. These results show a rather low variability with respect to other planar non-SOI advanced technologies [9]. The pMOS DUTs exhibit extra variability in minimum-length devices, which can be attributed to the interplay of line edge roughness and the short channel effect, as discussed in [10] and [11].…”

Section: Architecture Of the Test Array And Time-zero Variabilitymentioning

confidence: 69%

Comparative experimental analysis of time-dependent variability using a transistor test array

Simicic

Subirats

Weckx

et al. 2016

2016 IEEE International Reliability Physics Symposium (IRPS)

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As the minimum transistor length reaches the decananometer scale, both time-zero and time-dependent variability, the latter including Random Telegraph Noise (RTN) and Bias Temperature Instability (BTI), become a great concern for IC design. Accurate statistical models describing these two variability sources are therefore necessary in order to design reliable circuits and systems. This paper gives insights in the geometric scaling of these variabilities and analyzes timedependent variability through three different measurement techniques: 2-point Measure-Stress-Measure, Time-Dependent Defect Spectroscopy, and fine-step Id-Vg. Advantages and downsides of each technique are discussed and compared.

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Section: Architecture Of the Test Array And Time-zero Variabilitymentioning

confidence: 69%

Comparative experimental analysis of time-dependent variability using a transistor test array

Simicic

Subirats

Weckx

et al. 2016

2016 IEEE International Reliability Physics Symposium (IRPS)

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“…Additionally, literature data show that FinFET can provide additional 30% mismatch benefit for the same gate stack with respect to planar. 14,28) We have estimated the lateral area reduction that can be achieved in a S/A, assuming that the device will be converted from a planar HKMG into a FinFET HKMG platform. The assumption is that the FinFET will yield a 30% improved V T mismatch.…”

Section: Resultsmentioning

confidence: 99%

“…12,13) Therefore, Gate First integration seems more suitable for Memory application, and its feasibility has been proved by different teams. [14][15][16] After the planar HKMG, the next generation DRAM memories will require additional power-performance-areacost benefit, forcing the transition to a FinFET based platform offering additional power and performance benefit without adding significant cost. 17) In this work we have investigated the fabrication of FinFET devices specifically tailored for memory application, by extending the finding shown in Ref.…”

Section: Introductionmentioning

confidence: 99%

80 nm tall thermally stable cost effective FinFETs for advanced dynamic random access memory periphery devices for artificial intelligence/machine learning and automotive applications

Spessot¹,

Ritzenthaler²,

Litta³

et al. 2021

Jpn. J. Appl. Phys.

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Automotive, Artificial Intelligence/Machine Learning and blockchain generation are imposing increasing demanding specs for Dynamic Random Access Memory (DRAM) memories. Wider memory bandwidth can be achieved by using conventional planar SiO2 MOSFET and different interfaces but at the expense of required energy per bit. Advantages of High-K/Metal Gate versus SiO2/SiON planar DRAM periphery devices compatible with DRAM memory fabrication have been demonstrated in literature. More recently, the power performance benefit of FinFET for DRAM peri devices have been discussed. In this paper we provide a detailed analysis and additional insights in the first experimental validation of a thermally stable, reliable and cost effective tall fins platform (65 and 80 nm fin height). Power performance benefit versus fin height and expected area advantages on Sense Amp area are presented.

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“…We have successfully demonstrated three different HKMG process flow implementations, compatible with the DRAM requirements for transistors . In the following, we illustrate the various approaches.…”

Section: Gate Stack Optimizationmentioning

confidence: 99%

Optimized material solutions for advanced DRAM peripheral transistors

Spessot¹,

Ritzenthaler

Schram

et al. 2016

Physica Status Solidi (a)

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The fabrication of peripheral CMOS devices for DRAM memories requires specific optimization with respect to a standard logic flow, imposed by the additional constraints linked to the memory element fabrication. Several process tunings are needed to keep pace with the request for low leakage and low cost devices combined with the needs of highly performant and resilient circuits. In this article, we summarize the most significant developments achieved in recent years focusing on HKMG Gate stack, junction tuning, silicide optimization for DRAM peripheral transistors. Three different solutions with different fabrication complexity and performance for HKMG, optimized junction, and thermally stable NiPt silicide fabrication, all compatible with the DRAM requirements, are discussed.

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A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

Cited by 21 publications

References 27 publications

Comparative experimental analysis of time-dependent variability using a transistor test array

Comparative experimental analysis of time-dependent variability using a transistor test array

80 nm tall thermally stable cost effective FinFETs for advanced dynamic random access memory periphery devices for artificial intelligence/machine learning and automotive applications

Optimized material solutions for advanced DRAM peripheral transistors

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