80 nm tall thermally stable cost effective FinFETs for advanced dynamic random access memory periphery devices for artificial intelligence/machine learning and automotive applications

Spessot, A.; Ritzenthaler, R.; Litta, E. Dentoni; Dupuy, Emmanuel; O’Sullivan, Barry; Bastos, J.P.A.; Capogreco, E.; Miyaguchi, K.; Machkaoutsan, V.; Yoon, Y.; Fazan, P.; Horiguchi, N.

doi:10.35848/1347-4065/abebbf

Cited by 6 publications

(2 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In Figure 3 a,b, we assume the fin height is 80 nm. This fin height should be feasible and will be likely to be adopted for manufacturing in some future technological nodes [ 24 ]. For the FinFET structure, the folding ratio ranges from about 0.03 to about 0.087 for fin width increasing from 5 nm to 15 nm.…”

Section: Width Folding and Moore’s Law Scalingmentioning

confidence: 99%

On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node

Wong

Kakushima

2022

Nanomaterials

View full text Add to dashboard Cite

This work performs a detailed comparison of the channel width folding effectiveness of the FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire transistor (VNWFET) under the constraints of the same vertical (fin) height and layout footprint size (fin width) defined by the same lithography and dry etching capabilities of a foundry. The results show that the nanosheet structure has advantages only when the intersheet spacing or vertical sheet pitch is less than the sheet width. Additionally, for the nanowire transistors, the wire spacing should be less than 57% of the wire diameter in order to have a folding ratio better than a FinFET with the same total height and footprint. Considering the technological constraints for the gate oxide and metal gate thicknesses, the minimum intersheet/interwire spacing should be in the range of 7 to 8 nm. Then, the VNSFET structure has the advantage of boosting the chip density over the FinFET ones only when the sheet width is wider than 8 nm. On the other hand, the VNWFET structure may have a better footprint sizing than the FinFET ones only when the nanowire diameter is larger than 14 nm. In addition, considering the different channel mobilities along the different surface directions of the silicon channel and also some other unfavorable natures such as more complicated processes, more significant surface roughness scattering, and parasitic capacitance effects, the nanosheet transistor does not show superior scaling capability than the FinFET counterpart when approaching the ultimate technology node.

show abstract

Section: Width Folding and Moore’s Law Scalingmentioning

confidence: 99%

On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node

Wong

Kakushima

2022

Nanomaterials

View full text Add to dashboard Cite

show abstract

“…Breakthroughs in artificial intelligence using Deep Neural Networks (DNNs) have led recently to make autonomous driving at the forefront of goals of automotive industry [1]. However, when it comes to safety-critical applications like in autonomous driving, the advanced driver assistance systems inevitably demand Dynamic Random Access Memo-ries (DRAMs) to exhibit very low latency, high bandwidth [2], and extreme-low bit error rate [3] to fulfil tight reliability and performance constraints [4], [5]. The key challenge is that the harsh environments in which the operating temperatures go beyond 100 • C make electrics in vehicles extremely unreliable [6].…”

Section: Introductionmentioning

confidence: 99%

Longevity of Commodity DRAMs in Harsh Environments Through Thermoelectric Cooling

et al. 2021

View full text Add to dashboard Cite

Today, more and more commodity hardware devices are used in safety-critical applications, such as advanced driver assistance systems in automotive. These applications demand very high reliability of electronic components even in adverse environmental conditions, such as high temperatures. Ensuring the reliability of microelectronic components is a major challenge at these high temperatures. The computing systems of these applications rely on DRAMs as working memory, which are built upon bit cells that store charges in capacitors. These commodity DRAMs are optimized for cost per bit and not for high reliability. Thus, very high temperatures impose an enormous challenge for commodity DRAMs as the data retention time and reliability decrease largely, affecting the data correctness. Data correctness can be ensured up to certain temperatures by increasing the refresh rate to counterbalance the retention time reduction. However, this severely degrades the access latencies and the usable DRAM bandwidth. To overcome these limitations, we present for the first time a Thermoelectric Cooling (TEC) solution for commodity DRAMs in harsh-environments, such as automotive. Our TEC solution enables the use of commodity off-the-shelf DRAMs in safety-critical applications by reducing the temperature conditions to a range where they can operate reliably. This TEC solution is applied a posteriori to the DRAM chips without using high-cost package solutions. Thus, it maintains the low-cost targets of such devices, improves the reliability, and at the same time, counterbalances the adverse effects of increasing the refresh rate. To quantitatively evaluate the benefits of TEC on commodity DRAMs in harsh-environments, we performed system-level evaluations with several applications backed up by the measured data on commodity DRAMs. Our experimental results, using accurate multi-physics simulations that employ finite element method, demonstrate that the TECbased cooling ensures that the maximum temperature of all DRAM chips is always below 85°C despite that the original on-chip temperature (i.e., in the absence of our TEC based cooling) goes beyond 120°C.

show abstract

Thermal stability issue of ultrathin Ti-based silicide for its application in prospective DRAM peripheral 3D FinFET transistors

Liu

Gao

et al. 2021

J Mater Sci: Mater Electron

View full text Add to dashboard Cite

80 nm tall thermally stable cost effective FinFETs for advanced dynamic random access memory periphery devices for artificial intelligence/machine learning and automotive applications

Cited by 6 publications

References 18 publications

On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node

On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node

Longevity of Commodity DRAMs in Harsh Environments Through Thermoelectric Cooling

Thermal stability issue of ultrathin Ti-based silicide for its application in prospective DRAM peripheral 3D FinFET transistors

Contact Info

Product

Resources

About