A Low-Power High-Speed Hybrid ADC With Merged Sample-and-Hold and DAC Functions for Efficient Subranging Time-Interleaved Operation

Zahrai, Seyed Alireza; Zlochisti, Marina; Dortz, Nicolas Le; Onabajo, Marvin

doi:10.1109/tvlsi.2017.2739108

Cited by 18 publications

(10 citation statements)

References 35 publications

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“…The work in [32,33] exemplified the concept of a subranging time-interleaved architecture by realizing a hybrid flash TI-ADC with four time-interleaved CABS ADCs. This architecture employs a CABS ADC in a time-interleaved hybrid ADC configuration to take advantage of its power efficiency at relatively high speeds compared to conventional SAR ADCs.…”

Section: Architecture Case Studymentioning

confidence: 99%

“…A single-ended illustration of the ADC architecture from [32,33] is displayed in Figure 14. The architecture is a subranging ADC comprised of a 3-bit 1 GS/s flash ADC in the first stage and four time-interleaved 250 MS/s 5-bit CABS ADCs in the second stage.…”

Section: Architecture Case Studymentioning

confidence: 99%

“…Furthermore, driving the extra comparators would increase the power consumption in the clock generation circuitry. A foreground offset calibration method was developed [32,81] to achieve the low-power performance at the cost of area overhead. Since the calibration is offline, it does not increase the total power consumption.…”

Section: Controlcal Clk Sampcalmentioning

confidence: 99%

“…This subsection includes measurement setup details and explanations for the hybrid ADC example architecture discussed in Section 4.2 beyond the information in [32,33], which was fabricated in 130-nm CMOS technology and assembled in a TQFP128 package with a ground plane underneath. The full layout of the ADC is shown in Figure 17.…”

Section: Prototype Chip Layout and Testing Considerationsmentioning

confidence: 99%

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Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

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This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6-8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.

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Section: Architecture Case Studymentioning

confidence: 99%

Section: Architecture Case Studymentioning

confidence: 99%

Section: Controlcal Clk Sampcalmentioning

confidence: 99%

Section: Prototype Chip Layout and Testing Considerationsmentioning

confidence: 99%

See 2 more Smart Citations

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

Self Cite

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“…Subranging architectures can reduce the requirement of excessive amount of comparators. Additional strategies such as assisted low power ADCs and partial switching are used to improve the energy efficiency [9]- [14]. In [9], time interleaved architectures using capacitive based digital to analog converters (DAC) have been used.…”

Section: Introductionmentioning

confidence: 99%

Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

2019

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The sampling rate plays a key role in wireless applications at very high-frequency range. Flash analog-to-digital converter (ADC) betters the slow converter counterparts in this regard but bulky at inevitable high resolutions. A state-of-the-art Divide and Collate (DnC) algorithm is proposed to design the flash ADC at subranging levels. The offset voltage is kept at a minimum through the comparators used for novel coarse and fine conversion separately. The kick-back noise is also reduced by using sample and hold switches at the input. The 10-bit ADC architecture is designed with 45-nm CMOS technology and analyzed in the SPECTRE environment. A trivial variation in the transconductance with temperature is observed and consequently the offset drift with temperature is found to be 0.015 mV/ • C. The design improves the INL by 0.42 LSB and DNL by 0.3 LSB. Signal-tonoise-and-distortion (SNDR) ratio and spurious-free-dynamic-range (SFDR) are 51.8 dB and 62 dB respectively at a frequency range near the Nyquist rate with a supply voltage of 1 V and input frequency of 500 MHz. Subranging scheme minimizes the comparator requirements which is reflected in the 44% reduction in the power dissipation.

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An Area Effective and High Speed SAR ADC Architecture for Wireless Communication

Prathiba¹,

Santhi²

2020

Second International Conference on Computer Networks and Communication Technologies

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A Low-Power High-Speed Hybrid ADC With Merged Sample-and-Hold and DAC Functions for Efficient Subranging Time-Interleaved Operation

Cited by 18 publications

References 35 publications

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

An Area Effective and High Speed SAR ADC Architecture for Wireless Communication

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