A low-power, generic biostimulator with arbitrary pulse shape, based on a central control core

Faizollah, Milad; Karimi, Mousa; Sodagar, Amir M.

doi:10.1587/elex.10.20120868

Cited by 5 publications

(4 citation statements)

References 8 publications

(4 reference statements)

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“…During both transition times, when IN="0" or IN="1", MP2, MP4, and MN2-MN4 work 0 1 () Thus, the output of the presented LS changes when VA reaches VM. Therefore, when IN="1", to extract the rising PD (tpr) from ( 2), we replace iCp(t) by ITnM(t) that is described by (5). In this way, (2) can be rearranged as follows where V=VA.…”

Section: Cdmp4=cdsmp4+cdgmp4mentioning

confidence: 99%

“…Level shifters (LSs) are key circuits in numerous microelectronic systems including systems-on-chip (SoCs) and complex system-in-package (SiP) devices [1]- [4]. These circuits are used to translate one signal level to another, allowing signals to be properly transferred across different supply voltage domains [5]- [7]. High-performance telecommunication systems require high-speed LS circuits consuming as low power as possible.…”

Section: Introductionmentioning

confidence: 99%

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A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

et al. 2022

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A novel level shifter (LS) circuit that uses a new low-power approach based on a parasitic capacitance voltage controlled current source is presented to minimize the propagation delay (PD) and maximize the voltage conversion range. This new scheme uses a simplified circuit including a dependent current source, a composite transistor made of three interconnected n-channel MOSFETs (TnM), one CMOS input inverter, and one CMOS output buffer to provide a fast response time. The circuit utilizes the combined action of the equivalent parasitic capacitance of the TnM, the value of which changes dynamically according to the transient value of the input voltage, and the dependent current source to shift the input signal level up from subthreshold voltage levels to +3.0 V, with minimal delay and power consumption. The LS circuit fabricated in 0.35 µm CMOS technology occupies a silicon area of only 25 µm×25 µm. The LS shows measured rising and falling PDs of, respectively, 4 and 11.2 ns. The measured results show that the presented circuit outperforms other solutions over a wide frequency range of 1 to 130 MHz. The fabricated circuit consumes a static power 31.5 pW and a dynamic power of 3.4 pJ per transition at 1 kHz, VDDL=0.8 V, and a capacitive load of CL=0.1 pF.

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Section: Cdmp4=cdsmp4+cdgmp4mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

et al. 2022

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“…Moreover, analog I/Os with higher voltages (1.8V, 2.5V, and 3.3 V) are inevitable to allow proper interface between many different chips [12]. Thus, level shifters are essential circuits in both SoCs and SiPs to allow signal compatibility between all building blocks [13]- [17].…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Single-Supply Multiple-Level Down-Shifter for System-on-Chip Applications

Karimi

Ali

Hassan

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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A novel level down shifter intended for translation of signals with different amplitudes in System-on-Chip (SoC) applications is presented. This new single supply down-shifter architecture, implemented in a 0.35-µm AMS CMOS technology provides multiple reconfigurable levels. A diode connected circuit structure, a current source, five transmission gates, a diodesupercapacitor combination, and input/output buffers are employed to implement this reconfigurable level shifter. The circuit receives a pulse shaped signal with an amplitude of 3.3 V, and provides three different signals with nominal amplitudes of 1.2 V, 1.8 V, and 2.5 V depends on the circuit configuration. The proposed circuit successfully drives a range of capacitive loads between 10 fF and 350 pF. The presented circuit consumes a static and a dynamic power consumptions of 62.37 pW and 108.9μW, respectively from a 3.3V supply, at an operating frequency of 1 MHz and a capacitive load of 10 pF. Post-layout simulation results show that the fall and rise propagation delays of the three configurations are in the range of 0.54 ns-26.5 ns and 11.2 ns-117.2 ns, respectively. It occupies an area of 80 µm×100 µm.

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“…converters are mainly applied to system basis chips in automation, including those used in airbag squib drivers, braking valve drivers, and power steering integrated circuits [7]- [10]. Power converters are also widely used in neural stimulation and wireless power transmission in implantable biomedical microsystems [11]- [14].…”

mentioning

confidence: 99%

An Active Dead-Time Control Circuit With Timing Elements for a 45-V Input 1-MHz Half-Bridge Converter

Karimi

Ali

Hassan

et al. 2022

IEEE Trans. Circuits Syst. I

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In this study, a dead-time control circuit is proposed to generate independent delays for the high and low sides of halfbridge converter switches. In addition to greatly decreasing the losses of power converters, the proposed method mitigates the shoot-through current through the application of superimposed power switches. The circuit presented here comprises a switched capacitor architecture and is implemented in AMS 0.35 µm technology. In the implementation, the proposed dead-time control circuit occupies a silicon area of 70 µm × 180 µm. To realize the technique, a two-sided wide swing current source is employed. Each sides of the current source comes with two capacitors, two Schmitt triggers, and three transmission gates. Results show that the low and high sides of the projected half-bridge converter switches respectively require delays of 35 and 62 ns. The performance of the proposed dead-time circuit is evaluated by assembling it with the half-bridge converter. The proposed dead-time prototype achieves a 40% drop in power losses in the half-bridge circuit.

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A low-power, generic biostimulator with arbitrary pulse shape, based on a central control core

Cited by 5 publications

References 8 publications

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

A Reconfigurable Single-Supply Multiple-Level Down-Shifter for System-on-Chip Applications

An Active Dead-Time Control Circuit With Timing Elements for a 45-V Input 1-MHz Half-Bridge Converter

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