A Low-Power Frequency Multiplier for Multi-GHz Applications

Multi-data rate receiver for high-speed serial interfaces

“…Several performance characteristics of the CDR loop highly depend on the PI phase generation accuracy, while the demand for multi-rate high speed operation with low power consumption can increase its design complexity and make it challenging. Except for their adoption in CDRs, PIs are also used as phase rotators in PLL fractional-N dividers, as clock de-skew circuits in TX chains or multiphase generators in clock multipliers [25], [26], [27]. As a result, PIs had become a critical component, adopted in several important processes and blocks either in the receiver or the transmitter end, and increased the research interest for novel PI topologies, which offer higher resolution and precise phase generation under low power multi-rate operation environment.…”

“…In [148] a DLL-based multiplier is presented which includes two kind of D flip-flops and a pulse combining circuit with maximum output frequency around 2GHz. The multiplier of [149] which is based on AND-gates and pulse generators with an edge combiner is not suitable for high frequencies [26].…”

“…A wide range MPVCO-based frequency multiplier with a combination of programmable phase interpolator (PI) and edge combiner is proposed in this chapter. [151] but is limited for frequencies lower than 170MHz [26].…”

“…Also the proposed topology has been designed to be compliant with the MPHY multi-Gbps serial interface standard [30], the supported frequency Gears and Rates of which are presented in Table 7-1. By employing the proposed circuit and a single VCO with relatively small frequency range and center frequency of 0.624GHz, the required wide frequency range can be covered through frequency multiplications, relaxing in this way significantly the oscillator design complexity [26].…”

“…The block diagram of the proposed frequency multiplier is presented in Figure 7.1 and includes eight PI-Units, which actually implement a multi-segment programmable PI, an edge combiner and a toggle flip-flop. The top-level system comprises a voltagecontrolled ring oscillator which is the necessary MPVCO operating in the frequency of 0.624GHz [26]. The MPVCO contains 4 identical differential delay elements and produces 8 equitant clock phases from 0 o to 360 o with 45 o phase difference [135].…”