A Low-Power Efficient Direct Digital Frequency Synthesizer Based on New Two-Level Lookup Table

Yi, Shu-Chung; Lee, Kun-Tse; Chen, Jin-Jia; Lin, Chien-Hung

doi:10.1109/ccece.2006.277378

Cited by 5 publications

(3 citation statements)

References 6 publications

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“…For 16-bit DDFS, the SFDR of the proposed architecture is more than 86.85 dBc. As shown in Table 3 , the proposed DDFS is superior to the previous works in terms of SFDR, SNR, output resolution, and tuning latency [ 6 , 17 , 18 , 26 , 27 ]. According to the high performance of the proposed DDFS, it is very suited for medical instruments and body care network systems [ 46 – 49 ].…”

Section: Discussionmentioning

confidence: 90%

“…Several efficient compression techniques have been proposed to reduce the lookup table size [ 5 – 10 ]. The quadrant compression technique can compress the lookup table and then reduce the ROM size by 75% [ 6 ]. The Sunderland architecture splits the ROM into two smaller memories [ 7 ], and the Nicholas architecture improves the Sunderland architecture to achieve a higher ROM-compression ratio (32 : 1) [ 8 ].…”

Section: Introductionmentioning

confidence: 99%

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Optimization and Implementation of Scaling-Free CORDIC-Based Direct Digital Frequency Synthesizer for Body Care Area Network Systems

Juang

Chen

et al. 2012

Computational and Mathematical Methods in Medicine

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Coordinate rotation digital computer (CORDIC) is an efficient algorithm for computations of trigonometric functions. Scaling-free-CORDIC is one of the famous CORDIC implementations with advantages of speed and area. In this paper, a novel direct digital frequency synthesizer (DDFS) based on scaling-free CORDIC is presented. The proposed multiplier-less architecture with small ROM and pipeline data path has advantages of high data rate, high precision, high performance, and less hardware cost. The design procedure with performance and hardware analysis for optimization has also been given. It is verified by Matlab simulations and then implemented with field programmable gate array (FPGA) by Verilog. The spurious-free dynamic range (SFDR) is over 86.85 dBc, and the signal-to-noise ratio (SNR) is more than 81.12 dB. The scaling-free CORDIC-based architecture is suitable for VLSI implementations for the DDFS applications in terms of hardware cost, power consumption, SNR, and SFDR. The proposed DDFS is very suitable for medical instruments and body care area network systems.

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Section: Discussionmentioning

confidence: 90%

Section: Introductionmentioning

confidence: 99%

Optimization and Implementation of Scaling-Free CORDIC-Based Direct Digital Frequency Synthesizer for Body Care Area Network Systems

Juang

Chen

et al. 2012

Computational and Mathematical Methods in Medicine

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“…As the conventional DDS uses the look-up table (LUT) to store the trigonometric values, it requires large ROM and dissipates much more power. People have proposed some effective ways to solve the drawback, such as optimized LUT method [3] and adopting coordinate rotation digital computer (CORDIC) algorithm to calculate the trigonometric values in real time [4]. Compared to the LUT based DDS, the DDS based on CORDIC eliminates the ROM, and is more area efficient.…”

Section: Introductionmentioning

confidence: 99%

A low-power and high-SFDR Direct Digital Frequency Synthesizer based on adaptive recoding CORDIC

Zhang

Liu

2015

2015 IEEE 16th Annual Wireless and Microwave Technology Conference (WAMICON)

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Direct Digital Frequency Synthesizer (DDS) plays an important role in communication systems. In this paper, we propose a novel DDS architecture. Compared with the conventional lookup table (LUT) based DDS, the proposed one adopts the coordinate rotation digital computer (CORDIC) algorithm to accomplish phase-to-amplitude conversion. Due to the poor accuracy of the conventional CORDIC, an adaptive recoding CORDIC is proposed. To verify the correctness and evaluate the performance, the proposed DDS is validated on a Virtex 5 FPGA development platform. Compared with a commercial implementation of DDS, the power dissipation of the proposed DDS is reduced by 21.5% at the same toggle rate. Compared to the latest CORDIC based DDS, the spurious free dynamic range (SFDR) of the proposed DDS achieves 91.67 dBc and exceeds nearly 5 dBc.

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A ROM-less DDFS Based on a Parabolic Polynomial Interpolation Method with an Offset

Wang

Hsu

Lee

et al. 2010

J Sign Process Syst

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A novel direct digital frequency synthesizer (DDFS) based on a parabolic polynomial with an offset is proposed in this paper. A 16-segment parabolic polynomial interpolation is adopted to replace the traditional ROM-based phase-to-amplitude conversion methods. Besides, the proposed parabolic polynomial interpolation is realized in a multiplier-less structure such that the speed can be significantly improved. This work is manufactured by a standard 0.13 μm CMOS cell-based technology. The maximum clock rate is 161 MHz, the core area is 0.33 mm 2 , and the spurious free dynamic range (SDRF) is 117 dBc by physical measurements on silicon.Keywords Direct digital frequency synthesizer (DDFS) · Interpolation · Spurious free dynamic range (SFDR)

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A Low-Power Efficient Direct Digital Frequency Synthesizer Based on New Two-Level Lookup Table

Cited by 5 publications

References 6 publications

Optimization and Implementation of Scaling-Free CORDIC-Based Direct Digital Frequency Synthesizer for Body Care Area Network Systems

Optimization and Implementation of Scaling-Free CORDIC-Based Direct Digital Frequency Synthesizer for Body Care Area Network Systems

A low-power and high-SFDR Direct Digital Frequency Synthesizer based on adaptive recoding CORDIC

A ROM-less DDFS Based on a Parabolic Polynomial Interpolation Method with an Offset

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