A low power consumption CMOS differential-ring VCO for a Wireless Sensor

Thabet, Hanen; Meillere, S.; Masmoudi, Mohamed; Seguin, Jean-Luc; Barthélémy, H.; Aguir, Khalifa

doi:10.1109/newcas.2011.5981224

Cited by 13 publications

(3 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In addition, the use of external components in some publications like [9] gives qualities to the integrated circuits in terms of the consumption and noise performance of the circuits. The price to pay is the integration area.…”

Section: Most Publications Mentioned Inmentioning

confidence: 99%

Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy based on EKV3.0 Model

Ayed¹,

Ghariani²

2017

ijacsa

View full text Add to dashboard Cite

Abstract-In this paper, the design of micro-power CMOS ring VCO with minimum jitter intended for a concept of frequency synthesizer in biotelemetry systems is studied. A design procedure implemented in MATLAB is described for a circuit realization with TSMC 0.18μm CMOS technology. This conventional design methodology based on EKV3.0 model is clearly suited to the challenges of analog circuits design with reduced channel width. Measures realized with ADS confirmed methodology capability to circuit sizing respecting the specifications of application. The designed ring VCO operates at a central frequency of 433MHz in ISM band with an amplitude of oscillation equal to 500 mV. The integration area was intrinsic (without buffers and without external capacitances). The simulated phase noise is about -108 dBc/Hz at 1MHz, the value of rms jitter is 44.8 ps and the power consumption of the designed VCO is 6.37 mW @ 433 MHz.

show abstract

Section: Most Publications Mentioned Inmentioning

confidence: 99%

Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy based on EKV3.0 Model

Ayed¹,

Ghariani²

2017

ijacsa

View full text Add to dashboard Cite

show abstract

“…31 Many authors have proposed various differential delay cell VCOs in the literature, intending to improve the phase noise and decrease the power consumption and transistor counts. [32][33][34][35] In 1999, Park et al demonstrated a 900-MHz delay stage VCO based on 0.6 μm standard CMOS process. 36 Their proposed VCO showed a suitable phase noise, which made it a proper candidate for high-frequency applications.…”

Section: Introductionmentioning

confidence: 99%

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

Jooq

Bozorgmehr

Mirzakuchaki

2020

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryOver the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage‐controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high‐performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap‐gate transistors, this work aims to propose a carbon nanotube field‐effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10‐nm gate‐all‐around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA‐CNTFET‐based ring VCO consumes 85.176 μW at with a 6.12‐ to 10.42‐GHz frequency tuning range. At the worst‐case noise conditions, the proposed design presents ‐90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm2 physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA‐CNTFET‐based VCO can be considered as a potential candidate for X‐band satellite communication applications.

show abstract

“…Performance of these delay cells largely affects the performance of VCO circuit. Low power consumption, minimum chip area, low noise, high output frequency and ease of tuning are the demanding design parameters in VCO circuit design [20][21][22][23][24][25]. Further, higher level of integration and lesser power consumption makes the CMOS based ring oscillators a better candidate for on chip systems.…”

Section: Introductionmentioning

confidence: 99%

VCO Design using NAND Gate for Low Power Application

Kumar¹

2016

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

A low power consumption CMOS differential-ring VCO for a Wireless Sensor

Cited by 13 publications

References 12 publications

Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy based on EKV3.0 Model

Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy based on EKV3.0 Model

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

VCO Design using NAND Gate for Low Power Application

Contact Info

Product

Resources

About