A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-μm CMOS technology

Annovazzi, M.; Colonna, V.; Gandolfi, G.; Stefani, F.; Basçhirotto, A.

doi:10.1109/jssc.2002.1015679

Cited by 23 publications

(12 citation statements)

References 8 publications

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“…The main drawback of a multibit DDSM is the nonlinearity of the corresponding multibit DAC. This necessitates the use of linearization techniques such as dynamic element matching (DEM) to mitigate the consequences of the nonlinearity and to ensure that mismatches among the DAC elements do not corrupt the desired signal [14], [15]. In this paper, we focus on multibit digital delta-sigma modulation with sinusoidal inputs.…”

Section: Introductionmentioning

confidence: 99%

Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking—Part II: Non-Constant Input

Fitzgibbon

Kennedy

Maloberti

2012

IEEE Trans. Circuits Syst. I

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In this two-part paper, a design methodology for hardware reduction in digital delta-sigma modulators (DDSMs) based on bus-splitting and error masking is presented. Part I addresses Multi stAge noise SHaping (MASH) DDSMs with constant inputs; Part II focuses on error feedback modulators (EFMs) with time-varying inputs. In this paper, we address EFMs with DC inputs plus additive input least significant bit (LSB) dithering and show how hardware reduction can be achieved with minimal degradation of the output spectrum. We also address EFMs with sinusoidal inputs and show how bus-splitting and error masking techniques can be used to obtain a trade-off between the modulator complexity and the achievable signal-to-noise ratio.

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Section: Introductionmentioning

confidence: 99%

Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking—Part II: Non-Constant Input

Fitzgibbon

Kennedy

Maloberti

2012

IEEE Trans. Circuits Syst. I

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“…The crucial problem, however, is the need for a linear multi-bit D/A converter. Non-linearities can be reduced by the use of dynamic element matching algorithms associated with unitary sources [3]. Such algorithms increase the digital complexity, yet at the same time the analog part of the DAC requires a non negligible chip area.…”

Section: Introductionmentioning

confidence: 99%

Low-consumption sigma–delta DAC for audio mobile applications

Bénabès

Kielbasa

2008

Electron. Lett.

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“…High quality DVD audio and multimedia applications [1,4,7,13,14] require both high linearity and dynamic range. In addition, small die area and low power consumption are preferred in such applications for the reduced production and running cost.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, out-band noise must be attenuated to certain level. Additional detail requirements for audio digital-to-analog (DAC) applications are summarized in [1]. In such DAC designs, higher signal to noise and distortion ratio (SNDR) is much challenge to achieve than higher dynamic range (DR) is because of the presence of many nonlinearity sources.…”

Section: Introductionmentioning

confidence: 99%

“…For example, one audio DAC design [4] can achieve the 120-dB dynamic range and 102-dB SNDR, but at the cost of the high power consumption (> 50mW) since the 100 dB gain amplifier was used to drive the 600 Q load. In another multi-bit audio DAC design, less power (32.6mW) [1] was consumed to reach the 86-dB SNDR, but the driving load is too high (10-pf//4OkQ) to be applicable in audio applications.…”

Section: Introductionmentioning

confidence: 99%

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A Low Power, Low Distortion Single-bit Sigma-Delta Audio DAC with Distributed Feedback from Analog Output

Yan

2006

2006 49th IEEE International Midwest Symposium on Circuits and Systems

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A single-bit low power, low-distortion digital-toanalog converter (DAC) using distributed feedback structure for low output impedance audio application is presented. The current structure is a modified forth-order inversed follow-theleader feedback (IFLF) emphasizing on achieving high system performance with much reduced power consumption. This structure utilizes the distributed feedback from analog output to attenuate the nonlinear distortions from both the discrete time to continuous time interface and the output stage, and finite-impulse response (FIR) filter to attenuate the out-band quantization noise. The power consumption is reduced by the class-AB operation in the last stage OTA design. Systematic comparisons of the performance and power consumption are simulated by both Cadence and Matlab/Simulink. The results indicate that the proposed structure can achieve high SNDR with very low power consumption. Typically, the distortion can be attenuated at least by 95dB at 5 KHz input. To compare different DAC designs, the new Figure of Merit (FOM) is introduced and the current design shows significant improvement comparing the results in the literature. This proposed structure will be potentially useful for lowimpendence low-power audio applications.

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A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-μm CMOS technology

Cited by 23 publications

References 8 publications

Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking—Part II: Non-Constant Input

Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking—Part II: Non-Constant Input

Low-consumption sigma–delta DAC for audio mobile applications

A Low Power, Low Distortion Single-bit Sigma-Delta Audio DAC with Distributed Feedback from Analog Output

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