Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking—Part II: Non-Constant Input

Fitzgibbon, Brian; Kennedy, Michael Peter; Maloberti, Franco

doi:10.1109/tcsi.2012.2185278

Cited by 15 publications

(8 citation statements)

References 21 publications

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“…, r n−1 . The trade-off of the SNR against the parameters configurations have previously been reported in [94]. Thus, our contribution is the reduced hardware architecture, prop-EFMr 1 r 2 .…”

Section: Proposed Cascaded Error-feedback Modulatormentioning

confidence: 87%

“…r has a reduced-hardware complexity compared to prop-EFMr due to the fact that only l rn number of error bits are processed through the rth order loop filter. Furthermore, its hardware is significantly less compared to the previously reported implementation (where the EFMs are cascaded, as in [94]) because only the loop filters are cascaded instead of whole EFM stages. The comparison is presented in [Paper D].…”

Section: Proposed Cascaded Error-feedback Modulatormentioning

confidence: 98%

“…• A strategy to reduce the hardware of conventional ∆Σ has been devised recently that uses multiple cascaded modulation units [40,94]. A similar approach is devised in our work where we cascade several modified EFM units.…”

Section: Contributionmentioning

confidence: 99%

“…Then, the quantization operation on an arbitrary sample i of its input can be performed by scaling and rounding or truncating [94], as given by…”

Section: Quantization Processmentioning

confidence: 99%

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Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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Papers A and C are reprinted with permission from IEEE.Cover figure is an illustration of the digital cascaded error-feedback modulator.Printed by LiU-Tryck, Linköping, Sweden 2014 To my parents and teachers AbstractA number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit elementbased DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathev vi Abstract matically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry. Populärvetenskaplig sammanfattning vii viiiPopulärvetenskaplig sammanfattning I denna avhandling presenteras e...

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Section: Proposed Cascaded Error-feedback Modulatormentioning

confidence: 87%

Section: Proposed Cascaded Error-feedback Modulatormentioning

confidence: 98%

Section: Contributionmentioning

confidence: 99%

“…Then, the quantization operation on an arbitrary sample i of its input can be performed by scaling and rounding or truncating [94], as given by…”

Section: Quantization Processmentioning

confidence: 99%

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Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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“…A major challenge associated with the design of highresolution single-bit quantizer DDSMs is that they are highly tonal [13][14][15][16][17]. However, it is a well-known phenomenon that single-bit  D/A converters require significantly less hardware when compared to their multibit counterparts, as the latter need extra Dynamic Element Matching (DEM) circuitry [3], [18].…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of novel FPGA based time-interleaved variable centre-frequency digital Î£âˆ’Î” modulators

2015

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Multiresolution analog-to-digital converters (MRADC) are usually used in Time Domain ElectroMagnetic Interference (TDEMI) measuring systems for very fast signal sampling with a sufficient dynamic range. The properties of the spectrum measured by the TDEMI system influenced by imperfections in the MRADC are analyzed in this paper. Errors are caused by imperfect matching of the offset and gain and phase of the circuits used in parallel input channels typical for the MRADC. For deep analyses of MRADC behavior, a precise mathematical model has been created using the concept of additive error pulses. Furthermore, a dedicated process of the identification of discrepancy parameters from experimental data is proposed. Identified parameters enter the expressions of the model and enable side to side comparison of experimental and theoretical results.Novel, multi-path, time-interleaved digital sigma-delta modulators that can operate at any arbitrary frequency from DC to Nyquist are designed, analysed and synthesized in this study. Dual- and quadruple-path fourth-order Butterworth, Chebyshev, Inverse Chebyshev and Elliptical based digital sigma-delta modulators, which offer designers the flexibility of specifying the centre-frequency, pass-band/stop-band attenuation as well as the signal bandwidth are presented. These topologies are compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity to non-idealities. Detailed simulations performed at the behavioural-level in MATLAB are compared with the experimental results of the FPGA implementation of the designed modulators. The signal-to-noise ratios between the simulated and empirical results are shown to be different by not more than 3-5 dBs. Furthermore, this paper presents the mathematical modelling and evaluation of the tones caused by the finite wordlengths of these digital multi-path sigma-delta modulators when excited by sinusoidal input signals.

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Low Power, Low Area Digital Modulators using Gate Diffusion Input Technique

Askhedkar

Agrawal²

2019

Journal of King Saud University - Engineering Sciences

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Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking—Part II: Non-Constant Input

Cited by 15 publications

References 21 publications

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Design and implementation of novel FPGA based time-interleaved variable centre-frequency digital Î£âˆ’Î” modulators

Low Power, Low Area Digital Modulators using Gate Diffusion Input Technique

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