A Low Power 440-MHz Pulse-Swallow-Divider Combination Synchronization-Asynchronism-Hybrid Frequency Divider

Subthreshold Frequency Synthesis for Medical Implantable Transceivers

“…A summary of the power consumption for each of the major blocks is given in Table 5. (Kuo & Wu, 2006) 2400 and 5000 1.8 2.6 1.08 (0.18µm) (Kuo & Weng, 2009) 5141 to 5860 1.5 4.8 0.934 (0.18µm) (Lei et al, 2009) 500 to 3500 1.8 3.01 0.86 (0.18µm) (Pan et al, 2008) 1600 1.2 0.475 0.296 (0.18µm) (Kim et al, 2008) 3000 1.5 3.58 1.19 (0.18µm) (Zhang et al, 2009) 1700 1.5 3.2 1.88 (0.18µm) (Zhang et al, 2006) 440 1.8 0.54 1.23 (0.18µm) In order to perform the required function, the CLR signal is tied to the positive supply and the PRE signal is tied to the negative supply. The block diagram of the PDF is shown in Fig.…”