A high-speed low-power pulse-swallow divider with robustness consideration

Pan, Jie; Yang, Haigang; Yang, Ling

doi:10.1109/icsict.2008.4734998

Cited by 5 publications

(2 citation statements)

References 5 publications

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“…As a crucial component of the fractional-N frequency synthesizer, the frequency divider puts forward higher requirements. Therefore, a high operating speed and low power consumption fractional-N frequency divider are highly desired [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. The working speed limitation of pulse swallow frequency divider is determined by the delay time of MC signal (τ MC ) [1,2,3,20,21,22,23,24,25,26].…”

Section: Introductionmentioning

confidence: 99%

A modified pulse swallow frequency divider for fractional-N PLL

Yan

Jiang

Liu

et al. 2020

IEICE Electron. Express

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A modified pulse swallow frequency divider for fractional-N frequency synthesizers was designed and implemented in a 0.18 µm CMOS process. The proposed structure inserts a pulser between D flip-flop 1 (DFF1) and B counter to solve the possible malfunction of the SR latch and the unwanted division ratio offset in the conventional structure. To remarkably improve the operating speed, a D flip-flop 2 (DFF2) was employed to retime the modulus control (MC) signal. The proposed frequency divider can work at an input clock signal frequency up to 7.04 GHz with a power consumption of only 7.59 mW.

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Section: Introductionmentioning

confidence: 99%

A modified pulse swallow frequency divider for fractional-N PLL

Yan

Jiang

Liu

et al. 2020

IEICE Electron. Express

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show abstract

“…Also, employing a timing window generation by using a finite-width pulse generator was also known to be effective [3]. Nevertheless, these architectures [3,4] inherently possess an unwanted division ratio offset of one with relative timing and the possibility of malfunction of the SR latch in the structure.…”

Section: Introductionmentioning

confidence: 99%

A low-power CMOS programmable frequency divider with novel retiming scheme

Radhapuram

Bae

et al. 2015

IEICE Electron. Express

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Abstract:We propose a novel pulse-swallow programmable frequency divider with a D flip-flop for retiming. The proposed scheme reduces the critical delay path of the modulus control (MC) signal extending the MC timing margin. This enables the high-speed operation of the divider. Moreover, unlike the conventional retiming structure, the MC signal is set and reset by a single signal triggered reset circuitry to eliminate the unwanted division ratio offset and the possible malfunction of set-reset (SR) latch. Simulation results show that the proposed divider designed in 130-nm CMOS technology consumes 53 µW at 1-GHz operation frequency from a 0.7-V supply voltage. The proposed divider achieves the lowest power consumption among the previously reported dividers at GHz operations.

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An ultra-low power 200 MHz-1 GHz programmable frequency divider with novel clear/preset d-latch

Khan

Raahemifar

2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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A high-speed low-power pulse-swallow divider with robustness consideration

Cited by 5 publications

References 5 publications

A modified pulse swallow frequency divider for fractional-N PLL

A modified pulse swallow frequency divider for fractional-N PLL

A low-power CMOS programmable frequency divider with novel retiming scheme

An ultra-low power 200 MHz-1 GHz programmable frequency divider with novel clear/preset d-latch

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