A Low-Power 40-Gb/s Pre-Emphasis PAM-4 Transmitter With Toggling Serializers

Kwon, Do Young; Kim, M.; Kim, Sung-Geun; Choi, Woo-Young

doi:10.1109/tcsii.2019.2922040

Cited by 6 publications

(5 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this work, a VM driver similar to that of Ref. [5] was realized by CMOS inverters, as shown in Figure 3.…”

Section: ⅱ Implementation and Analysismentioning

confidence: 99%

“…Finally, a power amplifier is followed to transfer enhanced signal power to the mmWave antenna. Although the PAM4 signals synthesized by current mode logic (CML) or voltage mode (VM) driver have been reported, the VM drivers have better power efficiency and linearity compared to the CML ones [4,5] . In addition, due to the inherent 3X SNR degradation of PAM4 signaling and severe channel loss in high frequency band, it is essential to equalize the modulation circuit using feed-forward equalizer (FFE) technique.…”

Section: ⅰ Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design of PAM4 modulation circuit with 2-tap pre-emphasis for millimeter-wave application

Xie

Xue

Song

et al. 2023

Conference on Infrared, Millimeter, Terahertz Waves and Applications (IMT2022)

View full text Add to dashboard Cite

Millimeter-wave (mmWave) technology has been employed in many applications due to abundant bandwidth resources and high interference immunity such as telecommunication, automotive radars, and imaging. In this paper, a mmWave transmitter link incorporating PAM4 modulation, resonant tunneling diode (RTD) based oscillator, power amplifier and antenna was proposed. To achieve good linearity and alleviate inter-symbol interference (ISI) caused by channel loss simultaneously, a PAM4 modulation circuit utilizing voltage mode driver and 2-tap pre-emphasis was designed and optimized in TSMC 28 nm CMOS process. The simulation results show that our PAM4 modulation circuit operates properly at 40Gb/s with a differential output swing of up to 800 mVpp under a supply voltage of 0.9 V. The overall power consumption is about 51.3 mW, corresponding to an energy efficiency of 1.28 pJ/bit.

show abstract

“…In this work, a VM driver similar to that of Ref. [5] was realized by CMOS inverters, as shown in Figure 3.…”

Section: ⅱ Implementation and Analysismentioning

confidence: 99%

Section: ⅰ Introductionmentioning

confidence: 99%

Design of PAM4 modulation circuit with 2-tap pre-emphasis for millimeter-wave application

Xie

Xue

Song

et al. 2023

Conference on Infrared, Millimeter, Terahertz Waves and Applications (IMT2022)

View full text Add to dashboard Cite

show abstract

“…3 The power is for a single lane of the transmitter. 4 Energy Efficiency (mW/Gbps) = Power/Data Rate.…”

Section: Time(ps)mentioning

confidence: 99%

“…High-speed serializer/de-serializer (SerDes) technology is extensively employed to improve the data transmission performance of wireline transmission systems [1]. Due to the continuous development of data-intensive services, such as the Internet of Things, cloud computing, and cloud storage, telecommunication infrastructure is required to be upgraded; therefore, the requirements for the data transmission rate of SerDes should be increased [2][3][4][5]. Therefore, the transmitter of SerDes must provide a high-speed data transfer rate and maintain the signal integrity, which is the main problem faced in the design.…”

Section: Introductionmentioning

confidence: 99%

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

et al. 2022

View full text Add to dashboard Cite

An 8 gigabits per second (Gbps), low-jitter, four-channel transmitter with fractional-spaced feed-forward equalizer (FFE) is designed to meet the demand for broad transmission bandwidth in serial data communications. A novel frequency divider chain (FDC) architecture is developed, to satisfy the time requirements for high-speed data serialization. Moreover, a reconfigurable output driver circuit is employed to ensure compatibility with different protocols. In addition, a three-tap fractional-spaced FFE, which can enhance signal bandwidth significantly, is proposed, to compensate for channel loss. The transmitter was simulated and validated based on the Semiconductor Manufacturing International Corporation (SMIC) 55-nm process. The post-layout simulation results show the following: The tuning range of the phase-locked loop (PLL) can cover 1.6 to 4.6 GHz. At an output frequency of 4 GHz, the root-mean-square jitter (RJ) of the PLL after integration from phase noise was 1.93 ps. With an 8 Gbps output data rate, using the pseudo-random binary sequence (PRBS)-31 as a data source to simulate the whole transmitter, the power consumption values of the PLL and drive circuit were 27.0 and 29.2 mW, respectively, and the eye width and the valid eye height of output data were 0.76 unit interval (UI) and 0.68.

show abstract

“…Two techniques are widely exploited to improve data rates and energy efficiency. The four-level amplitude modulation technique (PAM-4) can mitigate the bandwidth requirements [1]- [3]. the digital domain equalization technique improves the attenuation compensation ability by using the AD/DA converter to perform complex calculations in the digital domain [4]- [7].…”

Section: Introductionmentioning

confidence: 99%

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver

Ding

Jin

Zhou

2022

IEICE Trans. Fundamentals

View full text Add to dashboard Cite

This brief presents A 16/32 Gb/s dual-mode transmitter including a linearity calibration loop to maintain amplitude linearity of the SST driver. Linearity detection and corresponding master-slave power supply circuits are designed to implement the proposed architecture. The proposed transmitter is manufactured in a 22nm FD-SOI process. The linearity calibration loop reduces the peak INL errors of the transmitter by 50%, and the RLM rises from 92.4% to 98.5% when the transmitter is in PAM4 mode. The chip area of the transmitter is 0.067 mm 2 , while the proposed linearity enhanced part is 0.05×0.02 mm 2 and the total power consumption is 64.6 mW with a 1.1 V power supply. The linearity calibration loop can be detached from the circuit without consuming extra power.

show abstract

A Low-Power 40-Gb/s Pre-Emphasis PAM-4 Transmitter With Toggling Serializers

Cited by 6 publications

References 7 publications

Design of PAM4 modulation circuit with 2-tap pre-emphasis for millimeter-wave application

Design of PAM4 modulation circuit with 2-tap pre-emphasis for millimeter-wave application

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver

Contact Info

Product

Resources

About