A low power 20 bit instrumentation delta-sigma ADC

Yamamura, K.; Nogi, Akihiko; Barlow, A.

doi:10.1109/cicc.1994.379669

Cited by 8 publications

(4 citation statements)

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“…In the integration phase, they are partially tied to and according to the DWA algorithm presented in Section III. Moreover, in order to increase the input impedance of the circuit, the input capacitors are first charged to input signals or reference voltage through input buffers [12]. Hence, each capacitor can be connected to eight different nodes:…”

Section: Practical Implementationmentioning

confidence: 99%

A 19-bit low-power multibit sigma-delta ADC based on data weighted averaging

Nys

Henderson

1997

IEEE J. Solid-State Circuits

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This paper describes a low-power multibit sigma-delta analog-to-digital converter (ADC) which achieves 19-b resolution. Multibit quantization and feedback within a sigma-delta loop are shown to provide a power-efficient solution for high-resolution converters. As the linearity of the digital-toanalog converter (DAC) in the feedback path is a critical issue, a comparison of different DAC solutions is made demonstrating the efficiency of the data weighted averaging algorithm. An implementation of this technique within a monolithic sigma-delta ADC is then described. The whole chip, including the digital decimation filter, consumes only 2.7 mW for an 800-Hz output rate. The resolution and linearity improvement brought by data weighted averaging is confirmed by measurements.

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Section: Practical Implementationmentioning

confidence: 99%

A 19-bit low-power multibit sigma-delta ADC based on data weighted averaging

Nys

Henderson

1997

IEEE J. Solid-State Circuits

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“…The delta-sigma (∆Σ) ADC is one architecture that is being examined for use in lowpower, high-resolution, moderate-speed applications. Conventionally, ∆Σ ADCs are used for low-frequency applications (< 100 kHz) requiring high resolution (> 14 bits), such as digital audio or high-precision instrumentation [1,2,3]. Recent work, however, is extending the signal bandwidths of ∆Σ ADCs into the MHz range while maintaining high resolution [4,5].…”

Section: Chapter 1 Introductionmentioning

confidence: 99%

“…Given that ω 0 = ω s /(2 • OSR) and that ω s = 2π, Equation (2.10) can be rewritten as follows: 3 (2.11) Figure 2.4 is a graphical comparison between the signals Q(ω) and N (ω) for a ∆Σ ADC with an oversampling ratio (OSR) of 16. Notice how little power of N (ω) exists in the signal band, which is all that will remain after low-pass filtering.…”

Section: Introduction To Delta-sigma Adcsmentioning

confidence: 99%

“…% initialization points OSR = 20; % oversampling ratio dacmmc = 0; % percent mismatch (in %) of coarse dac elements dacmmf = 0; % percent mismatch (in %) of fine dac elements sigbins = 1; % bins on either side of signal to lump with signal NODEM = 0; % set to 1 % ideal 2-step (coarse,fine) quantization using pre-calculated slope and % intercept values % in value to be quantized % mc coarse input multiplier before rounding % mf fine input multiplier before rounding % bc coarse input offset before rounding % bf fine input offset before rounding % maxc coarse output code is forced to be in range [0,maxc] % maxf fine output code is forced to be in range [0,maxf] % outc coarse output integer quantized value % outf fine output integer quantized value % dubout output double quantized value (with same input range as 'in') % dubc coarse quantized value (with same input range as 'in') % dubf fine quantized value (with same input range as 'in', but scaled % to be fine) outc = round(mc*in + bc); % 1st (coarse) quantization step outc = max( % power spectrum using fft cspec = cspec(2:pts/2+1); % only interested one side, forget dc semilogx(10*log10(cspec)); % plot it title('Single Element Course Power Spectra (corselm)'); xlabel('Frequency'); ylabel('Power'); subplot (2,2,3); fspec = (abs(fft(fineelm))).^2; % power spectrum using fft fspec = fspec(2:pts/2+1); % only interested one side, forget dc semilogx(10*log10(fspec)); % plot it title('Single Element Fine Power Spectra (fineelm)'); xlabel('Frequency'); ylabel('Power'); subplot(2,2,2); cspec = (abs(fft(yc))).^2; % power spectrum using fft cspec = cspec(2:pts/2+1); % only interested one side, forget dc semilogx(10*log10(cspec)); % plot it title('Course Output Power Spectra (yc)');…”

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confidence: 99%

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Dynamic element matching techniques for delta-sigma ADCs with large internal quantizers

Nordick

Petrie

Cheng

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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This thesis presents two methods that enable high internal quantizer resolution in delta-sigma analog-to-digital converters. Increasing the quantizer resolution in a delta-sigma modulator can increase SNR, improve stability and reduce integrator power consumption. However, each added bit of quantizer resolution also causes an exponential increase in the power dissipation, required area and complexity of the dynamic element matching (DEM) circuit required to attenuate digital-to-analog converter (DAC) mismatch errors. One way to overcome these drawbacks is to segment the feedback signal, creating a "coarse" signal and a "fine" signal. This reduces the DEM circuit complexity, power dissipation, and size. However, it also creates additional problems. The negative consequences of segmentation are presented, along with two potential solutions: one that uses calibration to cancel mismatch between the "coarse" DAC and the "fine" DAC, and another that frequency-shapes this mismatch error. Mathematical analysis and behavioral simulation results are presented. A potential circuit design for the frequency-shaping method is presented in detail. Circuit simulations for one of the proposed implementations show that the delay through the digital path is under 7 ns, thus permitting a 50 MHz clock frequency for the overall ADC. ACKNOWLEDGMENTS I would like to gratefully acknowledge the support and encouragement from my wife, Andrea. To her go the official titles of "Tech Writer" and "Hyphenation-Queen" for all the proofreading and grammar checking. (Any mistakes still present in this text are most likely because I made some changes and didn't ask her to check them over.) Special thanks to my wonderful parents for their support, and for providing a roof over our heads for a bit when it was needed. Thanks as well to my brothers and sisters for their examples in striving for advanced degrees. I would like to acknowledge Dr. Craig Petrie for the time he has taken to proofread and suggest improvements for the various drafts of this thesis. I also acknowledge the other two members of my graduate committee, Dr. Michael Rice and Dr. Brent Nelson, for their help with my thesis. Special thanks to all three for the instruction and mentoring they have provided during my time as a student at BYU.

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