A Low Power 2.5 Gbps 1:32 Deserializer in SiGe BiCMOS Technology

Tobajas, F.; Esper-Chain, R.; Regidor, R.; Santana, O.; Sarmiento, Roberto

doi:10.1109/ddecs.2006.1649564

Cited by 5 publications

(7 citation statements)

References 8 publications

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“…In the multimode filter [11] it is observed that more than 50 % of power is dissipated in the low complexity CIC filters. Since portable audio applications are very sensitive to power, it is proposed to move the critical subfilters to the analog full custom domain.…”

Section: Low Power Decimator For Portable Audio Applicationmentioning

confidence: 98%

“…This causes a major drawback for CIC filters with large M: high circuit activity and area requirements in the integrators, which need to operate at the high sample rate and with full w min , even for a 2 bit wide noise shaper output (containing ±1 or two's complement [01] b and [11] b ). Therefore, careful adjustment of data wordlengths is required.…”

Section: Implementation Of Cic Filtersmentioning

confidence: 99%

“…In all subfilters w j is adjusted such that the total additional quantization noise is less than the noise produced by the truncation to w out . Data arriving from a 1 bit quantizer contain ±1, for which two binary digits (w in = 2, [01] b and [11] b ) are required. For a full range operation an extension to w min = 2 + n · log 2 M is required at the input of the first integrator's adder stage.…”

Section: Implementation Of Cic Filtersmentioning

confidence: 99%

“…Registers 1-8 operate directly on the data and clock input and are not sensitive to the phase delays of the clock generator circuit and wire delays are much easier to control [11]. A gated input clock pulse is applied to registers 9-16 to form the input data streams for the following polyphase filter blocks at the reduced clock rate.…”

Section: Polyphase Decimator For High Speed Applicationsmentioning

confidence: 99%

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Multirate filter design and implementation for mixed-signal ICs

Ofner¹,

Zhang

Ley³

2015

Elektrotech. Inftech.

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This paper describes the design of multirate filters used for the sample rate reduction of digital signals and their implementation on mixed-signal integrated circuits. Reaching target specifications of power, speed and silicon area as well as realizing multi-mode operation presents challenges. Possible solutions are discussed particularly for those filter stages which operate at the high sample rates and are illustrated in examples. Entwurf von Multiratenfiltern für gemischt analog-digitale ICs. Dieser Artikel beschreibt den Entwurf von Multiratenfiltern zur Reduktion derTaktrate digitaler Signale in gemischt analog-digitalen ICs. Die Realisierung von Systemanforderungen im Bereich der Leistungsaufnahme, der Taktrate und Siliziumfläche sowie eines MultimodeBetriebs stellt dabei eine besondere Herausforderung dar. Lösungsansätze speziell für jene Filterstufen, die mit den hohen Taktraten arbeiten, werden anhand von Beispielen beschrieben.

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Section: Low Power Decimator For Portable Audio Applicationmentioning

confidence: 98%

Section: Implementation Of Cic Filtersmentioning

confidence: 99%

Section: Implementation Of Cic Filtersmentioning

confidence: 99%

Section: Polyphase Decimator For High Speed Applicationsmentioning

confidence: 99%

See 2 more Smart Citations

Multirate filter design and implementation for mixed-signal ICs

Ofner¹,

Zhang

Ley³

2015

Elektrotech. Inftech.

View full text Add to dashboard Cite

show abstract

“…5. 64:8 MUX is implemented with shift-register architecture for chip area reduction, while the other MUXs are based on tree structure for power reduction [3]. For testing 64:1 MUX with LC-PLL, 64-bit wide parallel pseudo-random bit stream 2 7 -1 (PRBS7) generator is integrated in front of 64:8 MUX.…”

Section: Cmentioning

confidence: 99%

A 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme

Park

Choi

Lee

et al. 2012

2012 IEEE International Symposium on Circuits and Systems

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In this paper, we report a 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme that can be used for long-haul optical transmission of various display standards. The serializer includes three clock-and-data-recovery circuits, de-multiplexers, a digital processing block, a phase-locked-loop, multiplexers, and optical front-end circuits. To eliminate the need for a wide-range phase-locked loop, the fixed-data-rate scheme is used. The ASIC produces 6.24-Gb/s serialized data from parallel input signals and, with them, drives a verticalcavity surface-emitting laser. The serializer ASIC occupies 3.45 mm 2 and consumes 151.7 mW.

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Fully integrated serial-link receiver with optical interface for long-haul display interconnects

Park

Lee

et al. 2012

IET Circuits, Devices &Amp; Systems

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We report a fully integrated serial-link receiver with optical interface fabricated with a 0.18 mm complementary metal oxide semiconductor technology for long-haul display interconnects. The receiver includes a trans-impedance amplifier, a limiting amplifier, a clock and data recovery circuit, 1:64 de-multiplexer and a built-in error checker. The receiver produces 64-bit wide electrical signals from photodetector output signals produced by 5.28, 5.6 or 6.25 Gb/s optical signals delivered through up to 700-m multi-mode fibre. It can support serialised data for UXGA Q1 , 1080 p and WUXGA. The receiver core occupies 0.59 mm 2 with 42.4 mW power dissipation at 6.25 Gb/s bit rate from a 1.8 V supply.

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A Low Power 2.5 Gbps 1:32 Deserializer in SiGe BiCMOS Technology

Cited by 5 publications

References 8 publications

Multirate filter design and implementation for mixed-signal ICs

Multirate filter design and implementation for mixed-signal ICs

A 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme

Fully integrated serial-link receiver with optical interface for long-haul display interconnects

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