A 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme

Abstract

In this paper, we report a 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme that can be used for long-haul optical transmission of various display standards. The serializer includes three clock-and-data-recovery circuits, de-multiplexers, a digital processing block, a phase-locked-loop, multiplexers, and optical front-end circuits. To eliminate the need for a wide-range phase-locked loop, the fixed-data-rate scheme is used. The ASIC produces 6.24-Gb/s serialized data from parallel input signals and, with them, drives a verticalcavity surface-emitting laser. The serializer ASIC occupies 3.45 mm 2 and consumes 151.7 mW.

A novel energy-efficient serializer design method for gigascale systems

“…With the similar timing analysis, as shown in condition 4, our hybrid serializer can achieve nearly twice data rate of the half-speed tree type, four times to the full-speed tree serializer. To satisfy the demands of high operating frequency, current-mode logic (CML) circuits have been extensively used in the serializer design [1]. CML circuits are faster than most of static CMOS circuits because the transistors operate only in the saturation or triode regions, and the output is not full-swing.…”

“…To achieve high-speed communication in gigascale systems, serializers have become one of the critical blocks in transceiver circuits, as shown in Figure 1. Recent work shows that current serializers can operate at 20+Gbps in large scale system on-chip (SoC) [1]. The increasing data rate inevitably results in dramatic power consumption.…”