2001
DOI: 10.1109/23.958755
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A low-power 10-bit ADC in a 0.25-/spl mu/m CMOS: design considerations and test results

Abstract: This paper presents the design and test of a low power analog-to-digital converter (ADC) implemented in a commercial 0.25 m CMOS technology. The circuit has been developed to serve as a building block in multichannel data acquisition systems for high energy physics (HEP) applications. Therefore, medium resolution (10 bits), very low power consumption, and high modularity are the key features of the design. In HEP experiments, the resistance of the electronics to the ionizing radiation is often a primary issue.… Show more

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Cited by 21 publications
(3 citation statements)
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“…The first two, PASCAL and AMBRA, are assembled on the front-end hybrid, shown in figure 3.19 on its assembly jig. PASCAL contains three functional blocks: preamplifier, analogue storage and Analogue-to-Digital Converter (ADC) [64][65][66][67]. AMBRA, which receives data from PASCAL, is a digital four-event buffer which performs data derandomisation, baseline equalization on an anode-by-anode basis and 10-bit to 8bit non-linear data compression.…”
Section: Sensor Layoutmentioning
confidence: 99%
“…The first two, PASCAL and AMBRA, are assembled on the front-end hybrid, shown in figure 3.19 on its assembly jig. PASCAL contains three functional blocks: preamplifier, analogue storage and Analogue-to-Digital Converter (ADC) [64][65][66][67]. AMBRA, which receives data from PASCAL, is a digital four-event buffer which performs data derandomisation, baseline equalization on an anode-by-anode basis and 10-bit to 8bit non-linear data compression.…”
Section: Sensor Layoutmentioning
confidence: 99%
“…Signal processing techniques being developed for processing the data from the detector [1,2] also call for a high sampling rate of the ADC -at least one sample per bunch-crossing (BC), which means 40 MS/s for typical LHC experiments [3,4]. Some effort was invested in dedicated ADC ASIC development for LHC applications in the past decade [5][6][7][8][9]. This brief will explore the potential of the successive-approximation-register (SAR) ADC implemented in deeply scaled bulk CMOS technology for the application of particle physics experiment.…”
Section: Introductionmentioning
confidence: 99%
“…The first two, PASCAL and AMBRA, are assembled on the front-end hybrid, shown in figure 3.19 on its assembly jig. PASCAL contains three functional blocks: preamplifier, analogue storage and Analogue-to-Digital Converter (ADC) [64][65][66][67]. AMBRA, which receives data from PASCAL, is a digital four-event buffer which performs data derandomisation, baseline equalization on an anode-by-anode basis and 10-bit to 8-bit non-linear data compression.…”
Section: Sensor Layoutmentioning
confidence: 99%