High-speed, high-resolution, radiation-tolerant SAR ADCs for particle physics experiments

Abstract

We present two CMOS 12-bit successive-approximation-register (SAR) analog-todigital converter (ADC) designs and the total dose irradiation test results of the second, a 12bit, 160-MS/s two-step SAR ADC in 40-nm CMOS. This second SAR ADC, which measured a 67.5-dB signal-to-noise plus distortion ratio (SNDR) and a >85-dB spurious-free dynamic range (SFDR), showed minimal degradation after being exposed to a total ionizing dose (TID) of up to 1 Mrad. The measured power consumption is 4.5 mW and 6.1 mW at 80 MS/s and 160 MS/s, respectively. The small silicon area of both ADCs also exhibits a great advantage for treating single event effects (SEE) using redundancy techniques, e.g., the triple modular redundancy (TMR), with much less concern for additional area overhead in a future upgrade than designs that occupy large silicon area. The experimental results reveal great potentials of SAR ADC implemented in scaled bulk CMOS process for the front-end digitizing applications of high-energy particle physics experiments.