A Low Phase Noise, Low Power and Wide Tuning Range VCO with Filtering Technique in ISM Band

Sabaghi, Masoud; Marjani, Saeid; Majdabadi, Abbas

doi:10.4236/cs.2016.72007

Cited by 4 publications

(2 citation statements)

References 25 publications

(15 reference statements)

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“…Furthermore, a highperformance multiprocessor platform has been used in the phases of coding, simulation, and verification as well as synthesizing and tests. The simulation results are given in tables (2-4|) along with figures (8)(9). The path delay results were generated using TimeQuest timing analyzer tool of Quartus II package with Fast 1200mV 0C Model and area estimation results were generated using Analysis and Synthesize tool after Post-Fitting Mapping and port assignments.…”

Section: Cost Factors Analysis and Synthesize Resultsmentioning

confidence: 99%

“…It contributes in almost every processors task to do complex computations such as the random number generators [6] and computation of greatest common divisor [7]. Also, in building cryptographic coprocessor as in elliptic curve cryptographic (ECC) design [8], low power applications [9] as in the tiny RSA Cryptoprocessor design [10], communication systems as in the MIMO System design in [11] and many other applications. Due to this significant role of adders, researchers of arithmetic computing and processing proposed extensive alternatives.…”

Section: Introductionmentioning

confidence: 99%

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Fpga Synthesis and Validation of Parallel Prefix Adders

Al‐Haija¹,

Asad²,

Marouf³

et al. 2019

Acta electron. Malays.

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The main objective of this paper is to attain the best achievable time delay reduction with better performance (i.e. frequency) running on FPGA platforms and prove their applicability in high performance reconfigurable computing in addition to evaluate the FPGA design area and thermal power dispassion. The paper presents description on the implementation of five fast radix-2 parallel prefix adders, namely: Ladner-Fischer Adder (LFA), Brent-Kung Adder (BKA), Kogge-Stone Adder (KSA), Hans-Carlson Adder (HCA), and Sklansky Adder (SkA), with variable data path sizes ranging from 8 bits to 64 bits. The PPA topologies were implemented using VHDL description language and synthesized using Altera Cyclone IV E (EP4CE115 F29C7) FPGA chip device. Intensive tests and verifications were conducted and analyzed validate and evaluate the design cost factors: total path delay time, maximum frequency, design area and the total FPGA thermal power dissipations of the FPGA design as well as the hardware utilization. The results on the code synthesizing demonstrated that the proposed FPGA implementation of KSA has recorded the best values of critical path delay with 4.504 ns for 64 bits while BKA recorded the least design area results with 223 logic elements for the same bit length. In terms of power dissipation, KSA and SkA adders have recorded the best outcomes since they consume the minimum total thermal power dissipation among all other PPAs and for all bit lengths. Thus, the performance of the proposed PPA adders was benchmarked against other state-of-the-art designs which results reflected its superiority in terms of throughput of two or more multiple times as compared to others.

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Section: Cost Factors Analysis and Synthesize Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fpga Synthesis and Validation of Parallel Prefix Adders

Al‐Haija¹,

Asad²,

Marouf³

et al. 2019

Acta electron. Malays.

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A comparative performance analysis of CMOS XOR XNOR circuits

Sharma¹,

Kumre²

2017

2017 International Conference on Recent Innovations in Signal Processing and Embedded Systems (RISE)

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Novel Quantum Structure of an III-V Tunneling Field-Effect Transistor with Source and Channel Heterojunction

Sabaghi

2020

HOLOS

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In this work, an III-V tunneling field-effect transistor (TFET) with source and channel heterojunctions is proposed and introduced. Proposed structure combine the high tunneling efficiency induced by heterojunction material and the high mobility of III-V material. The III-V TFETs based on either source heterojunction and channel heterojunctions have been intensively researched due to their excellent subthreshold-swing characteristics. However, compared with conventional III-V TFETs, the III-V TFETs with source and channel heterojunctions have both shorter tunneling distance and two transmission resonances that significantly improve the on-current. The transfer characteristics affected by gate length were also evaluated. The results show that on-current, off-current, and on-current/off-current ratio and subthreshold-swing of III-V TFETs with source and channel heterojunctions are about 10 -3 A/µm, 10 -13 A/µm, 10 -10 and 30 mV/decade, respectively.

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A Low Phase Noise, Low Power and Wide Tuning Range VCO with Filtering Technique in ISM Band

Cited by 4 publications

References 25 publications

Fpga Synthesis and Validation of Parallel Prefix Adders

Fpga Synthesis and Validation of Parallel Prefix Adders

A comparative performance analysis of CMOS XOR XNOR circuits

Novel Quantum Structure of an III-V Tunneling Field-Effect Transistor with Source and Channel Heterojunction

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