A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

Abiri, Ebrahim; Salehi, Mohammad Reza; Salem, Sanaz

doi:10.1016/j.mejo.2014.04.009

Cited by 8 publications

(3 citation statements)

References 30 publications

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“…In a special frequency band, the block is used to select the desired channels in the band. As shown in Figure 1, the synthesizer consists of phase frequency detector (PFD), charge pump (CP), voltage-controlled oscillator (VCO), and frequency divider subblocks [2]. The VCO block that produces the desired frequency is one of the most important synthesizer subblocks.…”

Section: Introductionmentioning

confidence: 99%

Low power and low phase noise VCO with dual current shaping for IoT applications

Nejadhasan¹,

Moazenian²,

Abiri³

et al. 2020

Turk J Elec Eng & Comp Sci

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In this paper, two low phase noise and power consumption VCO circuits, which are suitable for Internet of things (IoT) applications, are proposed. In the first structure, in order to have more control of the current consumption, the current shaping technique is used in the PMOS and NMOS biasing circuit. In the second structure, for increasing the oscillation amplitude and reducing the phase noise, independent biasing for the NMOS section is used. In both structures, to increase the frequency tuning range (FTR), without using a capacitor bank, the varactor is used in the biasing structure. In the first structure the supply voltage, output frequency, power consumption, and phase noise are 0.8 V, 2.44 GHz, 0.37 mW, and-117.5 dBc/Hz, respectively, but in the second structure, the supply voltage, output frequency, power consumption, and phase noise are 0.8 V, 2.44 GHz, 0.62 mW, and-120 dBc/Hz, respectively. It should be noted that the two structures are designed and simulated in 65-nm CMOS technology. Finally, the results show that the figure-of-merit for the first and second structures is-190 dBc/Hz and-190.2 dBc/Hz, respectively.

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Section: Introductionmentioning

confidence: 99%

Low power and low phase noise VCO with dual current shaping for IoT applications

Nejadhasan¹,

Moazenian²,

Abiri³

et al. 2020

Turk J Elec Eng & Comp Sci

Self Cite

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“…Voltage controlled oscillator (VCO) is one of the essential blocks in mixed‐signal‐systems such as phased locked loop (PLL), delayed locked loop and clock data recovery (CDR). It generates oscillating signals in which oscillation frequency is controlled by the voltage [1, 2]. Since it plays an important role in the analogue and digital applications, it should tolerate many kinds of faults especially in harsh environment.…”

Section: Introductionmentioning

confidence: 99%

Fault‐tolerant delay cell for ring oscillator application in 65 nm CMOS technology

Salem

Zandevakili

Mahani

et al. 2018

IET Circuits, Devices & Systems

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A novel fault tolerant delay cell for ring oscillator (RO) is proposed. As RO is one of the crucial blocks in phased locked loop, delayed locked loo and clock data recovery, it should be tolerated against single event transient (SET) and stuck at faults for harsh environment. Their proposed hybrid fault tolerant topology is combination of triple and quad transistors redundancy, which is applied to the delay cell structure based on the sensitivity role of each transistor. The simulation results with Cadence software show that the proposed fault-tolerant delay cell dissipates 34.34 µW power, while it occupies 127.2 µm 2 chip area. The proposed topology not only has lower power dissipation in comparison with existing fault tolerant delay cells but also is more reliable against stuck at single and multiple faults and also SETs. By using the proposed reliable delay cell in the RO, the achieved power dissipation and phase noise are about 249 µW and −96 dBc/Hz, respectively, while higher reliability is achieved in comparison with non-redundant RO s.

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“…The design of fractional frequency synthesizers (FFS) on an integrated circuit is an extensively explored research topic [1][2][3]. These circuits are very important in wireless communications and clock recovery circuits [4], thus the design and simulation strategies for these circuits are still of interest.…”

Section: Introductionmentioning

confidence: 99%

A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment

González-Díaz¹,

Muñoz‐Pacheco²,

Espinosa-Flores-Verdad³

et al. 2016

RADIOENGINEERING

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A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

Cited by 8 publications

References 30 publications

Low power and low phase noise VCO with dual current shaping for IoT applications

Low power and low phase noise VCO with dual current shaping for IoT applications

Fault‐tolerant delay cell for ring oscillator application in 65 nm CMOS technology

A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment

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