A low-parasitic collector construction for high-speed SiGe:C HBTs

Abstract

We present a new collector construction for high-speed SiGe:C HBTs that substantially reduces the parasitic base-collector capacitance by selectively underetching of the collector region. The impact of the collector module on RF performance is demonstrated in separate bipolar processes for npn and pnp devices. A minimum gate delay of 3.2ps was achieved for CML ring oscillators with npn transistors featuring fT/ f , , values of 300GHd250GHz at BVCEo = 1 AV. For pnp devices with fT/ f, , , values of 135GHz I140GHr at BVCEO = 2.W a gate delay of 5 . 9~~ is demonstrated. Further vertical scaling of the doping profiles increases fT to 380GHz at BVcEo = 1.5V for npn's and 155GHz at BVcEo = 2.3V for pnp's, but ring oscillator speed and fmax degraded.

Novel Collector Structure Enabling Low-Cost Millimeter-Wave SiGe:C BiCMOS Technology

“…4, with a peak f T /f MAX of ~200/320GHz. This f MAX is the highest known value for a SiGe:C HBT without buried layer/epi and deep trench modules [10], [11]. The slopes are near ideal (-20dB/dec), showing f T /f MAX of ~200/320GHz (extrapolation from the slope), in agreement with the extrapolations at a fixed frequency.…”

SiGe HBTs featuring fT ≫400GHz at room temperature

“…Regarding the C B E B C HBT, record f T values of 410GHz and 640GHz were measured at 294K and 35K respectively, the collector current density J C at peak f T , being larger than 20mA/µm². To the authors' knowledge, this is the first demonstration of a SiGe HBT transit frequency above 400GHz at room temperature [11], [12]. Transistors parameters at 294K and 35K are summarized in Table I.…”

SiGe HBT technology with f<inf>T</inf>/f<inf>max</inf> of 300GHz/500GHz and 2.0 ps CML gate delay

“…Here, we do not subtract R E because of missing standard measuring conditions. For the CML ring oscillator (RO) measurements, we used a configuration with 53 stages at 300mV voltage swing as in (12).…”