A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC

Baird, R.T.; Fiez, T.S.

doi:10.1109/4.494193

Cited by 50 publications

(16 citation statements)

References 11 publications

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“…To our purpose, we can consider an essentially constant decimation filter power consumption. By adding up all the contributions, the power dissipation of the M can be estimated as Power (24) …”

Section: Appendix Power Estimator For Cascade Msmentioning

confidence: 99%

Highly Linear 2.5-V CMOS>tex<$Sigma Delta $>/tex<Modulator for>tex<$hboxADSL+$>/tex<

Rı́o

Rosa

Pérez-Verdú

et al. 2004

IEEE Trans. Circuits Syst. I

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We present a 90-dB spurious-free dynamic range sigma-delta modulator (61M) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-m CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within 0.85 and 0.80 LSB 14 b , respectively. The 61 modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the 61 modulator.Index Terms-Analog-to-digital converter (ADC), asymmetric digital subscriber line (ADSL), MASH, sigma-delta modulation, switched-capacitor circuits.

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Section: Appendix Power Estimator For Cascade Msmentioning

confidence: 99%

Highly Linear 2.5-V CMOS>tex<$Sigma Delta $>/tex<Modulator for>tex<$hboxADSL+$>/tex<

Rı́o

Rosa

Pérez-Verdú

et al. 2004

IEEE Trans. Circuits Syst. I

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“…Partial solutions to these problems have been reported elsewhere. For instance, the internal DAC nonlinearity can be corrected through calibration, either in the analog domain [3], or in the digital domain [4]. A different approach is offered by the dual-quantization in one converter [5].…”

Section: Introductionmentioning

confidence: 99%

A low-power multi-bit delta-sigma modulator for audio signal processing

Liou

Lin

Yeh

et al. 2009

2009 Fourth International Conference on Communications and Networking in China

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A low-power high-resolution oversampled 4-bit delta-sigma modulator is designed in this paper. The 2 nd -order multi-bit modulator can achieve 14-bit resolution of 24 KHz signal bandwidth when oversampling rate of 128 is used. Fully differential switched capacitor is used to accomplish the modulator. The quantizer is made by a 17-level flash analog-todigital converter. Dynamic element matching technique is used to minimize the capacitor mismatch problem. Data weighted averaging (DWA) can increase SNR by 30 dB when capacitor mismatch is 1% symmetrical linear gradient distribution. SNR improvement with DWA technique is studied on several different capacitor mismatch distribution functions, such as random, linear, and curved distributions. The operational voltage of modulator is 1.8 V, and TSMC 0.25-μm CMOS process is used for the fabrication of this modulator. The modulator with DWA function becomes less sensitive to process variation. The measured SNR of the modulator is 84.3 dB and the power consumption of the modulator is 9.3 mW.

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“…Consumer quality Hi-Fi audio needs to be digitized at 16 bits of resolution, and audiophiles prefer up to 18-20 bits of resolution. The high-resolution conversion realized using this architecture is obtained by trading off speed for accuracy, which results in resolutions that far exceed the IC process component matching [1,2,3]. The trade-off of speed for resolution is a key aspect of delta-sigma converters.…”

Section: Introductionmentioning

confidence: 99%

A Fourth-Order 18-b Delta-Sigma A/D Converter

Jim

Changlu

Guan-huai

2005

2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis

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Oversampled analog-to-digital converters (ADCs) are attractive for VLSI implementation because they are especially tolerant of circuit nonidealities and component mismatch. For higher-order sigma-delta ( -) modulators, the multistage noise shaping technique (MASH)modulator architectures are often to be adopted to avoid instability problems. A CMOS 18-b fourth-order Sigmadelta ADC is described in the paper. The integrated circuit contains a fourth-order delta-sigma modulator and decimation filters. With an oversampling ratio of 128 and a clock rate of 6.4 MHz, simulations show that the ADC achieves a dynamic range of 109dB and a peak SNR of 108.2dB over a 22 kHz bandwidth.

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A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC

Cited by 50 publications

References 11 publications

Highly Linear 2.5-V CMOS>tex<$Sigma Delta $>/tex<Modulator for>tex<$hboxADSL+$>/tex<

Highly Linear 2.5-V CMOS>tex<$Sigma Delta $>/tex<Modulator for>tex<$hboxADSL+$>/tex<

A low-power multi-bit delta-sigma modulator for audio signal processing

A Fourth-Order 18-b Delta-Sigma A/D Converter

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A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC

Cited by 50 publications

References 11 publications

Highly Linear 2.5-V CMOS&gt;tex&lt;$Sigma Delta $&gt;/tex&lt;Modulator for&gt;tex&lt;$hboxADSL+$&gt;/tex&lt;

Highly Linear 2.5-V CMOS&gt;tex&lt;$Sigma Delta $&gt;/tex&lt;Modulator for&gt;tex&lt;$hboxADSL+$&gt;/tex&lt;

A low-power multi-bit delta-sigma modulator for audio signal processing

A Fourth-Order 18-b Delta-Sigma A/D Converter

Contact Info

Product

Resources

About

Highly Linear 2.5-V CMOS>tex<$Sigma Delta $>/tex<Modulator for>tex<$hboxADSL+$>/tex<

Highly Linear 2.5-V CMOS>tex<$Sigma Delta $>/tex<Modulator for>tex<$hboxADSL+$>/tex<