A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures

Fernández-Pascual, Ricardo; Garcia, Jose M.; Acacio, Manuel E.; Duato, J.

doi:10.1109/hpca.2007.346194

Cited by 25 publications

(31 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This enables a transaction to drop an earlier grant response that may have been stuck in the network. This process is very similar to the token re-creation process in the reliable token cache coherence protocol described in [16] and we expand more on that analogy in the next sub-section. We do not reproduce the minor implementation details [16] of that process here for space reasons.…”

Section: Protocol Extensions To Handle Message Lossmentioning

confidence: 99%

“…Therefore, it is important that on-chip communication protocols also be designed to handle message loss. This is a problem that is starting to gain prominence [6,16,27,40].…”

Section: Designing Reliable Protocolsmentioning

confidence: 99%

“…These messages are part of the baseline cache coherence protocol. A separate solution (such as those described in [16,27]) is required to handle message loss in the cache coherence protocol and is orthogonal to the focus of this paper (the algorithm to determine when a transaction can proceed with propagating its updates) 4 . The above changes to the protocol do not introduce any additional traffic when there is no message loss (assuming that the timeout window is long enough and there are few false alarms).…”

Section: Protocol Extensions To Handle Message Lossmentioning

confidence: 99%

“…In this work, we do not worry about error resilience within the cache coherence protocol -that issue is orthogonal to the problem of error resilience within the HTM commit algorithms. Techniques to make the cache coherence protocol error-resilient can be based on the work in [16,27].…”

Section: Designing Reliable Protocolsmentioning

confidence: 99%

See 3 more Smart Citations

Scalable and reliable communication for hardware transactional memory

Pugsley

Awasthi

Madan

et al. 2008

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques

View full text Add to dashboard Cite

In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true for a large-scale distributed memory system where multiple transactions may attempt to commit simultaneously and coordination is required before allowing commits to proceed in parallel. In this paper, we propose novel algorithms to implement commit that are more scalable in terms of delay and are free of deadlocks/livelocks. We show that these algorithms have similarities with the token cache coherence concept and leverage these similarities to extend the algorithms to handle message loss and starvation scenarios. The proposed algorithms improve upon the state-of-the-art by yielding up to a 7X reduction in commit delay and up to a 48X reduction in network messages for commit. These translate into overall performance improvements of up to 66% (for synthetic workloads with average transaction length of 200 cycles), 35% (for average transaction length of 1000 cycles), and 8% (for average transaction length of 4000 cycles). For a small group of multi-threaded programs with frequent transaction commits, improvements of up to 8% were observed for a 32-node simulation.

show abstract

Section: Protocol Extensions To Handle Message Lossmentioning

confidence: 99%

“…Therefore, it is important that on-chip communication protocols also be designed to handle message loss. This is a problem that is starting to gain prominence [6,16,27,40].…”

Section: Designing Reliable Protocolsmentioning

confidence: 99%

Section: Protocol Extensions To Handle Message Lossmentioning

confidence: 99%

Section: Designing Reliable Protocolsmentioning

confidence: 99%

See 2 more Smart Citations

Scalable and reliable communication for hardware transactional memory

Pugsley

Awasthi

Madan

et al. 2008

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques

View full text Add to dashboard Cite

show abstract

“…Other proposals have explored token counting in the context of multi-socket multi-core systems [23], virtual hierarchical coherence [25], fault-tolerant coherence [9,26], and multicast interconnection networks [14].…”

Section: Background On Token Countingmentioning

confidence: 99%

Token tenure: PATCHing token counting using directory-based cache coherence

Raghavan

Blundell

Martin

2008

2008 41st IEEE/ACM International Symposium on Microarchitecture

View full text Add to dashboard Cite

Follow this and additional works at: http://repository.upenn.edu/cis_reports Token tenure: PATCHing token counting using directory-based cache coherence Raghavan, A.; Blundell, C.; Martin, M.M.K. Copyright 2008 IEEE. Reprinted from MICRO-41. 41st IEEE/ACM International Symposium on Microarchitecture, 8-12 Nov. 2008 ,pages 47-58. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. Traditional coherence protocols present a set of difficult tradeoffs: the reliance of snoopy protocols on broadcast and ordered interconnects limits their scalability, while directory protocols incur a performance penalty on sharing misses due to indirection. This work introduces PATCH (Predictive/Adaptive Token Counting Hybrid), a coherence protocol that provides the scalability of directory protocols while opportunistically sending direct requests to reduce sharing latency. PATCH extends a standard directory protocol to track tokens and use token counting rules for enforcing coherence permissions. Token counting allows PATCH to support direct requests on an unordered interconnect, while a mechanism called token tenure uses local processor timeouts and the directorypsilas per-block point of ordering at the home node to guarantee forward progress without relying on broadcast. PATCH makes three main contributions. First, PATCH introduces token tenure, which provides broadcast-free forward progress for token counting protocols. Second, PATCH deprioritizes best-effort direct requests to match or exceed the performance of directory protocols without restricting scalability. Finally, PATCH provides greater scalability than directory protocols when using inexact encodings of sharers because only processors holding tokens need to acknowledge requests. Overall, PATCH is a ldquoone-size-fits-allrdquo coherence protocol that dynamically adapts to work well for small systems, large systems, and anywhere in between. CommentsToken tenure: PATCHing token counting using directory-based cache coherence Raghavan, A.; Blundell, C. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this d...

show abstract

Fault Tolerant Computer Architecture

Sorin

2009

Synthesis Lectures on Computer Architecture

View full text Add to dashboard Cite

A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures

Abstract: Abstract

Cited by 25 publications

References 17 publications

Scalable and reliable communication for hardware transactional memory

Scalable and reliable communication for hardware transactional memory

Token tenure: PATCHing token counting using directory-based cache coherence

Fault Tolerant Computer Architecture

Contact Info

Product

Resources

About