A Low-Noise High Input Impedance Analog Front-End Design for Neural Recording Implant

Huynh, Hai Au; Ronchini, Margherita; Rashidi, Amin; Tohidi, Mohammad; Farkhani, Hooman; Moradi, Farshad

doi:10.1109/icecs46596.2019.8964899

Cited by 13 publications

(5 citation statements)

References 11 publications

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“…The comparison results with other works are also shown in Table III. The maximal gain value in this paper is 71dB, meanwhile, the maximal gain value of [28] is 70 dB. The maximal gain value of [29] was 80dB, but the frequency range was less than 1kHz.…”

Section: Resultsmentioning

confidence: 59%

Design of a 1.8-µVrms IRN 180-dB CMRR configurable low-noise 6-channel analog front-end for neural recording systems on 180nm CMOS process

Pham

2023

IEICE Electron. Express

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This paper presents a configurable analog front-end (AFE) for low-power neural recording systems that is capable of the current-to-voltage converter, programmable gain, ultra-high input impedance, low-noise, and wide bandwidth. A 6-channel AFE consisting of 6 1-channel AFEs is also introduced in this paper. The proposed AFE is designed on a 180nm CMOS process for low noise and operates over a wide frequency range of 0.5 Hz to 2.3 kHz with low input-referred noise of 1.8 µVrms and the maximal CMRR value of 180 dB. The power consumption is 8.5 µW per channel.

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Section: Resultsmentioning

confidence: 59%

Design of a 1.8-µVrms IRN 180-dB CMRR configurable low-noise 6-channel analog front-end for neural recording systems on 180nm CMOS process

Pham

2023

IEICE Electron. Express

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“…The impedances are reported at 100 Hz. In [8], they utilize buffer at the input nodes to increase the input impedance. This technique was at the cost of loosing NEF and PEF.…”

Section: Simulation Resultsmentioning

confidence: 99%

High Input Impedance Capacitively-coupled Neural Amplifier and Its Boosting Principle

Shad

Naderi²,

Molinas

2020

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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This article proposes a technique for increasing the input impedance of conventional capacitively-coupled neural amplifiers based on careful examination of its analytical model. Following the precise derivation of the input impedance model, the effect of a negative capacitor is exploited as boosting principle to the input impedance of capacitively-coupled neural amplifiers. In order to implement this negative capacitor, some modifications were made to the conventional structure to make them suitable for capacitively-coupled neural amplifiers. The boosting factor which is calculated after these modifications exhibits frequency dependant parameters which offers further flexibility in the design and tuning. The proposed method to improve the input impedance is tested through simulation in a commercially available 0.18 µm CMOS technology. The robustness of the proposed structure is tested through Monte Carlo simulation in the presence of mismatch and process variation. Although the input impedance dropped with a factor of 2 during Monte Carlo simulations, the proposed method can still boost the input impedance by a factor of 100 at 100 Hz. While the proposed method might increase the area consumption, it maintains power efficiency property. When the proposed neural amplifier is compared to the state-of-the-art in terms of noise, power and input impedance, it shows relatively higher input impedance with negligible effect on input referred noise and power consumption which makes this structure suitable for low-power applications.

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“…Conversely, the DC-input architecture described in [ 312 ] for in vitro applications and in [ 281 , 313 ] for in vivo recordings were successfully demonstrated as a minimum area solution for highly-scalable neuroelectronic interfaces. In parallel, an important outcome of this research effort on front-end electronics for neural signals recording are low-power integrated circuit components that can be used in compact hybrid platforms to advance the interfacing of passive electrode arrays for a broad range of applications, including electroencephalography EEG recording systems [ 314 , 315 ] or BoC.…”

Section: Brain-on-chip Electrophysiology: Fabrication Features Anmentioning

confidence: 99%

Electrophysiology Read-Out Tools for Brain-on-Chip Biotechnology

et al. 2021

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Brain-on-Chip (BoC) biotechnology is emerging as a promising tool for biomedical and pharmaceutical research applied to the neurosciences. At the convergence between lab-on-chip and cell biology, BoC couples in vitro three-dimensional brain-like systems to an engineered microfluidics platform designed to provide an in vivo-like extrinsic microenvironment with the aim of replicating tissue- or organ-level physiological functions. BoC therefore offers the advantage of an in vitro reproduction of brain structures that is more faithful to the native correlate than what is obtained with conventional cell culture techniques. As brain function ultimately results in the generation of electrical signals, electrophysiology techniques are paramount for studying brain activity in health and disease. However, as BoC is still in its infancy, the availability of combined BoC–electrophysiology platforms is still limited. Here, we summarize the available biological substrates for BoC, starting with a historical perspective. We then describe the available tools enabling BoC electrophysiology studies, detailing their fabrication process and technical features, along with their advantages and limitations. We discuss the current and future applications of BoC electrophysiology, also expanding to complementary approaches. We conclude with an evaluation of the potential translational applications and prospective technology developments.

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A Low-Noise High Input Impedance Analog Front-End Design for Neural Recording Implant

Cited by 13 publications

References 11 publications

Design of a 1.8-µVrms IRN 180-dB CMRR configurable low-noise 6-channel analog front-end for neural recording systems on 180nm CMOS process

Design of a 1.8-µVrms IRN 180-dB CMRR configurable low-noise 6-channel analog front-end for neural recording systems on 180nm CMOS process

High Input Impedance Capacitively-coupled Neural Amplifier and Its Boosting Principle

Electrophysiology Read-Out Tools for Brain-on-Chip Biotechnology

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