2019
DOI: 10.1587/elex.16.20190494
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A low-loss high-linearity SOI SP6T antenna switch using diode biasing method

Abstract: This letter describes a single-pole six-throw (SP6T) antenna switch in a 180 nm silicon-on-insulator (SOI) CMOS technology for receive diversity and LTE transmit/receive applications. Using a new diode biasing method, the conventional biasing resistor and supply voltage are removed at the body of the stacked-FET switch, a diode is used to connect the body and gate for body bias instead. The biasing diode turns off and on and functions as a high and small resistor for the on and off state. The proposed design h… Show more

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Cited by 5 publications
(4 citation statements)
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References 28 publications
(27 reference statements)
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“…For the case of the CMOS SOI switch with a single-branch structure based on multi-stacked FET, it has the advantage of improving the power handling capability compared to that of the two cases mentioned above, due to the mitigated drain-source voltage (V ds.Mn ) of the single-FET, as shown in Figure 2 [4][5][6][7]. If the shunt branch is in the off-state condition, single-FETs are considered to be a simple capacitive equivalent circuit composed of symmetrical parasitic capacitances ('C gs ≈ C gd ' and 'C bs ≈ C bd ') between each node because of the symmetrical drain-source structure and floating gate/body condition, which is implemented by the gate/body resistors (R G , R B , R GC , R BC ) of tens of kilo-ohm or more (see Figure 2).…”
Section: Power Handling Capability and Linearity Of The Tunermentioning
confidence: 99%
“…For the case of the CMOS SOI switch with a single-branch structure based on multi-stacked FET, it has the advantage of improving the power handling capability compared to that of the two cases mentioned above, due to the mitigated drain-source voltage (V ds.Mn ) of the single-FET, as shown in Figure 2 [4][5][6][7]. If the shunt branch is in the off-state condition, single-FETs are considered to be a simple capacitive equivalent circuit composed of symmetrical parasitic capacitances ('C gs ≈ C gd ' and 'C bs ≈ C bd ') between each node because of the symmetrical drain-source structure and floating gate/body condition, which is implemented by the gate/body resistors (R G , R B , R GC , R BC ) of tens of kilo-ohm or more (see Figure 2).…”
Section: Power Handling Capability and Linearity Of The Tunermentioning
confidence: 99%
“…The growing diversity of modes, frequency bands, and mobile communication standards in modern smart terminals leads to an increased demand for integrated radio frequency (RF) switches. The primary antenna switch is responsible for connecting the primary antenna to the main cellular multi-mode multi-band (MMMB) transceiver [1,2,3,4]. Designing the primary antenna switch presents a significant challenge as it involves accommodating numerous parallel radio paths within a confined physical space, while maintaining low insertion loss (IL) with excellent isolation and linearity across different channels over a broad frequency range.…”
Section: Introductionmentioning
confidence: 99%
“…High-quality antenna switches are key building blocks for these transceivers, to establish multiple paths and meet the demands of multiple frequency bands and a wide array of specifications such as insertion loss (IL), isolation (ISO), power handling capacity, and linearity in MB, MS, and MM mobile applications [4], both for transmitter (Tx) and receiver (Rx) paths.  The conventional approach to high-power switch design is mostly based on gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) [5,6,7,8], silicon-on sapphire (SOS) [9], and silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technologies [10,11,12]. However, both GaAs and SOS technologies need expensive substrate and extra CMOS-based digital circuits.…”
Section: Introductionmentioning
confidence: 99%