2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS) 2018
DOI: 10.1109/iolts.2018.8474076
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A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays

Hossein Bardareh
1
,
Amir M. Hajisadeghi
2
,
Hamid R. Zarandi
3
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DUSTER: DUal Source Write TERmination Method for STT-RAM Memories

Faraji1,
Talafy
2
,
Hajisadeghi
3
et al. 2018
2018 21st Euromicro Conference on Digital System Design (DSD)
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DUSTER: DUal Source Write TERmination Method for STT-RAM Memories

Faraji1,
Talafy
2
,
Hajisadeghi
3
et al. 2018
2018 21st Euromicro Conference on Digital System Design (DSD)
3
0
0
0
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MOMENT: A Cross-Layer Method to Mitigate Multiple Event Transients in Combinational Circuits

Hajisadeghi
1
,
Bardareh
2
,
Zarandi
3
2018
2018 21st Euromicro Conference on Digital System Design (DSD)
4
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Bit Error Mitigation Using Unequal Resistivity Levels in Memristors

Hajisadeghi
1
,
Pourmomen
2
,
Zarandi
3
2022
2022 30th International Conference on Electrical Engineering (ICEE)
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