A Low Complexity-High Throughput QC-LDPC Encoder

Mahdi, Ahmed; Paliouras, V.

doi:10.1109/tsp.2014.2314435

Cited by 19 publications

(23 citation statements)

References 33 publications

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“…To quantify the underlying area complexity, a full-parallel architecture has been implemented [25] [24]. This architecture is based on hardwired XOR gates; the bits of each input vector, corresponding to non-zero elements of the matrix by which they are multiplied, are XORed to determine the resultant vector, as shown in Fig.…”

Section: Performance Of the Proposed Construction Methodsmentioning

confidence: 99%

“…. are implemented using one multiplication unit based on a rotating circuit followed by an accumulator, since all the non-zero sub-matrices are monomial shifted identity matrices [24]. As depicted in Fig.…”

Section: A Impact Of the Proposed Methods On Wifi And Wimax Qc-ldpc Cmentioning

confidence: 99%

“…To demonstrate the impact of the proposed method on the density of these matrices, and the hardware complexity of the corresponding LDPC encoder, we use the following algorithm and its full-parallel implementation as a complexity evaluator [24]. Let H 1 and H 2 be sub-matrices of H, of size m × k and m × m, respectively,…”

Section: Ldpc Encodingmentioning

confidence: 99%

“…The number of these types increases with the value of q, requiring additional memory to store them [24]. …”

Section: A Structure Of Pcm and Encoding Of Qc-ldpc Codesmentioning

confidence: 99%

“…7 depends completely on the number of non-zero elements of the involved matrices. Detailed and extended comparisons of this architecture to prior art are presented in [24] showing the benefits of the architecture. The algorithm employed in [24] XOR gates only.…”

Section: Prior Art -Complexity Reduction Due To the Proposed Polynmentioning

confidence: 99%

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On the Encoding Complexity of Quasi-Cyclic LDPC Codes

Mahdi

Paliouras

2015

IEEE Trans. Signal Process.

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In this paper we propose a parity check matrix (PCM) construction technique that reduces the encoding complexity of Quasi-Cyclic (QC)-LDPC codes. The proposed construction method is based on a constraint selection of shifting factors, shown here to reduce the density of an inverted matrix used in several encoding algorithms. Furthermore, it demonstrates that the complexity of encoding schemes involving inverted matrices, can be defined by the density of the small inverted binary base matrix and not by the extended QC-PCM. Comparisons of the proposed codes with codes employed in international standards and with randomly shifted QC-LDPC codes of comparable characteristics, show the low complexity of the corresponding hardware implementations and a BER performance equivalent to that of previously reported codes without increasing the decoding complexity. Furthermore, adoption of the proposed method can decrease the complexity of several encoding procedures; in particular, an area reduction of 40%-55% is reported for QC-LDPC encoders, while a reduction of 86% is reported for Multi-Level-QC-LDPC encoders. Index TermsLDPC encoding, quasi-cyclic LDPC, matrix inversion, density reduction, hardware architecture, encoding complexity, BER performance.A. Mahdi and V. Paliouras are with the VLSI Design IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. , NO. , , and Urbanke, RU [2] demonstrated that, if the PCM is approximate lower (or upper) triangular, the encoding complexity can be largely reduced by performing the encoding directly exploiting the sparse PCM. Most recently-proposed low-complexity encoder hardware design schemes [3]-[5] essentially follow this idea.For the practical LDPC coding system implementations, it has been shown that the conventional code and encoder and/or decoder design approach, i.e., first construct the code and then develop the encoder/decoder hardware implementations, should be revised. In fact, substantial complexity-related benefits occur if the code construction and encoder/decoder hardware implementation are jointly considered. The essence of joint code-architecture design is to apply certain implementation-oriented constraints on the LDPC code construction to simplify the LDPC encoder/decoder hardware implementations. Such a concept has been recently followed by Xia et al. [6], where the PCM has been constructed exploiting characteristics of permutation matrices to reduce the complexity and latency of encoding caused by multiplications by inverse matrices in the RU encoding scheme. In order to reduce hardware complexity, structured codes have been exploited by confining code constructions. A class of such LDPC codes are the Quasi-Cyclic (QC)-LDPC codes. QC-LDPC codes have the advantage of linear encoding time and reduced decoding complexity. A QC-PCM is composed of circulant sub-matrices, each is defined by a particular permutation value, called shifting value. Such codes can be encoded efficiently by using shift registers [7]-[9], and their decoder architecture requires simple address genera...

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Section: Performance Of the Proposed Construction Methodsmentioning

confidence: 99%

Section: A Impact Of the Proposed Methods On Wifi And Wimax Qc-ldpc Cmentioning

confidence: 99%

Section: Ldpc Encodingmentioning

confidence: 99%

“…The number of these types increases with the value of q, requiring additional memory to store them [24]. …”

Section: A Structure Of Pcm and Encoding Of Qc-ldpc Codesmentioning

confidence: 99%

Section: Prior Art -Complexity Reduction Due To the Proposed Polynmentioning

confidence: 99%