A Low-Area Direct Memory Access Controller Architecture for a RISC-V Based Low-Power Microcontroller

Morales, Hanssel; Duran, Ckristian; Roa, Elkim

doi:10.1109/lascas.2019.8667579

Cited by 7 publications

(4 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Ma et al [1], Paraskevas et al [31], and Rossi et al [11] present high-performance DMAEs ranging in size from 82 kGE to over 1.5 MGE. On the contrary, DMAEs designed for accelerating accesses to chip peripherals, as shown in the works of Pullini et al [38] and Morales et al [39] trade-off performance for area efficiency by minimizing buffer space [38] and supporting only simpler onchip protocols like AHB [39] or OBI [38]. Our iDMA can be parameterized to achieve peak performance as a highbandwidth engine in HPC systems, see Section 3.5, as well as to require less area (<2 kGE) than the ultra-lightweight design of Pullini et al's µDMA [38].…”

Section: Related Workmentioning

confidence: 99%

“…DMAEs can be grouped according to their system binding: register, transfer-descriptor, and instruction-based. Engines requiring a high degree of agility [11], [30] or featuring a small footprint [33], [38], [39] tend to use a registerbased interface. PEs write the transfer information in a dedicated register space and use a read or write operation to a special register location to launch the transfer.…”

Section: Related Workmentioning

confidence: 99%

“…SoC DMAEs, e.g., Fjeldtvedt et al [30], Rossi et al [11], and Morales et al [39] feature a fixed configuration of onchip protocol(s). Some controllers allow selectively adding a simple interface to connect to peripherals.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

A High-Performance, Energy-Efficient Modular DMA Engine Architecture

Benz,

Rogenmoser,

Scheffler

et al. 2024

IEEE Trans. Comput.

View full text Add to dashboard Cite

Data transfers are essential in today's computing systems as latency and complex memory access patterns are increasingly challenging to manage. Direct memory access engines (DMAEs) are critically needed to transfer data independently of the processing elements, hiding latency and achieving high throughput even for complex access patterns to high-latency memory. With the prevalence of heterogeneous systems, DMAEs must operate efficiently in increasingly diverse environments. This work proposes a modular and highly configurable open-source DMAE architecture called intelligent DMA (iDMA), split into three parts that can be composed and customized independently. The front-end implements the control plane binding to the surrounding system. The mid-end accelerates complex data transfer patterns such as multi-dimensional transfers, scattering, or gathering. The back-end interfaces with the on-chip communication fabric (data plane). We assess the efficiency of iDMA in various instantiations: In high-performance systems, we achieve speedups of up to 15.8× with only 1 % additional area compared to a base system without a DMAE. We achieve an area reduction of 10 % while improving ML inference performance by 23 % in ultra-low-energy edge AI systems over an existing DMAE solution. We provide area, timing, latency, and performance characterization to guide its instantiation in various systems.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

A High-Performance, Energy-Efficient Modular DMA Engine Architecture

Benz,

Rogenmoser,

Scheffler

et al. 2024

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…The DMA automaton splits into the reading and writing sections, where each one contains request and response counters. Once each automaton is triggered, it pushes the 128-bit block or the output of the AES to the DMA, which indirectly access the memory bus in the SoC [11]. A state machine controls the writing and reading datapath with five states.…”

Section: Aes Core Base Linementioning

confidence: 99%

AES Sbox Acceleration Schemes for Low-Cost SoCs

Duran

Gomez

Roa

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

View full text Add to dashboard Cite

Current solutions for low-cost and secure systems have ended up trading effective encryption schemes for lighter encryption schemes to ensure longevity in battery-powered applications. Here we demonstrate the potential to apply an effective and lighter encryption scheme, such as AES-256, in a low-cost battery-powered systems-on-chip (SoC) without demanding excessive energy. We accelerated AES-256 with a custom instruction along with an enhanced memory access scheme. Measurement results from a fabricated SoC featuring a RISC-V based 32-bit processor indicate a 900 fold improvement of AES-256 computing energy efficiency compared to pure-software implementations. The memory access improves the energy by 3 times an standard push-pull hardware implementation.

show abstract

Design and Implementation of the Link-List DMA Controller for High Bandwidth Data Streaming

Chiu

Liu

et al. 2022

Communications in Computer and Information Science

View full text Add to dashboard Cite

A Low-Area Direct Memory Access Controller Architecture for a RISC-V Based Low-Power Microcontroller

Cited by 7 publications

References 6 publications

A High-Performance, Energy-Efficient Modular DMA Engine Architecture

A High-Performance, Energy-Efficient Modular DMA Engine Architecture

AES Sbox Acceleration Schemes for Low-Cost SoCs

Design and Implementation of the Link-List DMA Controller for High Bandwidth Data Streaming

Contact Info

Product

Resources

About