AES Sbox Acceleration Schemes for Low-Cost SoCs

Abstract

Current solutions for low-cost and secure systems have ended up trading effective encryption schemes for lighter encryption schemes to ensure longevity in battery-powered applications. Here we demonstrate the potential to apply an effective and lighter encryption scheme, such as AES-256, in a low-cost battery-powered systems-on-chip (SoC) without demanding excessive energy. We accelerated AES-256 with a custom instruction along with an enhanced memory access scheme. Measurement results from a fabricated SoC featuring a RISC-V based 32-bit processor indicate a 900 fold improvement of AES-256 computing energy efficiency compared to pure-software implementations. The memory access improves the energy by 3 times an standard push-pull hardware implementation.

Low area and high throughput implementation of advanced encryption standard hardware accelerator on FPGA using Mux‐Demux pair

“…The papers in References 14,15,18,22 use a Virtex-7 FPGA board and the proposed work output is better compared to these works in terms of area. Research Work 19 mainly concentrates on enhancing the memory access and this structure consumes an area of 6791 slices. The less number of slices in Our Work-MDP1 is due to the implementing only one round and using the same slices for other rounds repeatedly instead of implementing every round which is a common practice for most of the previous works.…”

“…The papers in References 14,15,18,22 use a Virtex‐7 FPGA board and the proposed work output is better compared to these works in terms of area. Research Work 19 mainly concentrates on enhancing the memory access and this structure consumes an area of 6791 slices.…”

“…Duran et al in Reference 19 have demonstrated an effective and lighter encryption scheme in order to increase the memory access without demanding excess energy. An increase in memory access of three times more compared to standard hardware is achieved in this paper.…”