A Low-Area and Low-Power Comma Detection and Word Alignment Circuits for JESD204B/C Controller

Yin, Peng; Shu, Zhou; Xia, Yingjun; Shen, Tianmei; Guan, Xiao; Wang, Xiaoqin; Mohammad, Umar; Zang, Jiandong; Fu, Dongbing; Zeng, Xiaoping; Tang, Fang; Bermak, Amine

doi:10.1109/tcsi.2021.3072772

Cited by 6 publications

(2 citation statements)

References 19 publications

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“…The JESD204 protocol, proposed by JEDEC, has gradually replaced CMOS and LVDS as the mainstream data transmission solution between converter devices and logic devices [32]. Researchers have achieved multi-channel data transmission alignment by utilizing the system reference edge [33] and the deterministic latency characteristics of the JESD204B/C protocols [34][35][36]. In addition, some researchers have alleviated the pressure of synchronous design by integrating converters and radio frequency components [37][38][39].…”

Section: Introductionmentioning

confidence: 99%

Pulse Compression Shape-Based ADC/DAC Chain Synchronization Measurement Algorithm with Sub-Sampling Resolution

Hao,

Fang,

Luo

et al. 2024

Sensors

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In this article, we address the problem of synchronizing multiple analog-to-digital converter (ADC) and digital-to-analog converter (DAC) chains in a multi-channel system, which is constrained by the sampling frequency and inconsistencies among the components during system integration. To evaluate and compensate for the synchronization differences, we propose a pulse compression shape-based algorithm to measure the entire delay parameter of the ADC/DAC chain, which achieves sub-sampling resolution by mapping the shape of the discrete pulse compression peak to the signal propagation delay. Moreover, owing to the matched filtering in the pulse compression process, the algorithm exhibits good noise performance and is suitable for wireless scenarios. Experiments verified that the algorithm can achieve precise measurements with sub-sampling resolution in scenarios where the signal-to-noise ratio (SNR) is greater than −10 dB.

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Section: Introductionmentioning

confidence: 99%

Pulse Compression Shape-Based ADC/DAC Chain Synchronization Measurement Algorithm with Sub-Sampling Resolution

Hao,

Fang,

Luo

et al. 2024

Sensors

View full text Add to dashboard Cite

show abstract

“…As the data centers rapidly evolve to accommodate higher information transfer rates, a high-speed serial interface has become the main candidate to deliver data transmission [1][2][3][4][5][6][7]. Therefore, multiple industrial standards and protocols have been introduced, such as JESD204B, Thunderbolt, Peripheral Component Interconnect Express, and Universal Serial Bus [8][9][10][11]. The bandwidth requirements of those protocols keep increasing, and the decreased unit interval (UI) period becomes a bottleneck in high-speed transmitter (TX) design, which makes the timing budget extremely tight.…”

Section: Introductionmentioning

confidence: 99%

A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

et al. 2021

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This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane’s data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

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Area and power optimization approach for mixed polarity Reed–Muller logic circuits based on multi-strategy bacterial foraging algorithm

Zhou

Wang

et al. 2022

Applied Soft Computing

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A Low-Area and Low-Power Comma Detection and Word Alignment Circuits for JESD204B/C Controller

Cited by 6 publications

References 19 publications

Pulse Compression Shape-Based ADC/DAC Chain Synchronization Measurement Algorithm with Sub-Sampling Resolution

Pulse Compression Shape-Based ADC/DAC Chain Synchronization Measurement Algorithm with Sub-Sampling Resolution

A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Area and power optimization approach for mixed polarity Reed–Muller logic circuits based on multi-strategy bacterial foraging algorithm

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