A logarithmic response CMOS image sensor with on-chip calibration

Kavadias, S.; Dierickx, B.; Scheffer, Danny; Alaerts, A.; Uwaerts, Dirk; Bogaerts, Jan

doi:10.1109/4.859503

Cited by 186 publications

(90 citation statements)

References 3 publications

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“…It used logarithmic image sensors in order to reach high DR and FPN was also compensated. In year 2000, S. Kavadias reported a technique to remove the high FPN, due to its logarithmic response [86]. This CMOS image sensor, which was based on an active pixel structure, employed on-chip calibration and achieved a DR of 120 dB and the FPN was 2,5% of the output signal range.…”

Section: High Dynamic Range (Dr)mentioning

confidence: 99%

Review of CMOS image sensors

Bigas

Cabruja

Salví

2006

Microelectronics Journal

487

230

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The role of CMOS Image Sensors since their birth around the 1960s, has been changing a lot. Unlike the past, current CMOS Image Sensors are becoming competitive with regard to Charged Couple Device (CCD) technology. They offer many advantages with respect to CCD, such as lower power consumption, lower voltage operation, on-chip functionality and lower cost. Nevertheless, they are still too noisy and less sensitive than CCDs.Noise and sensitivity are the key-factors to compete with industrial and scientific CCDs. It must be pointed out also that there are several kinds of CMOS Image sensors, each of them to satisfy the huge demand in different areas, such as Digital photography, industrial vision, medical and space applications, electrostatic sensing, automotive, instrumentation and 3D vision systems.In the wake of that, a lot of research has been carried out, focusing on problems to be solved such as sensitivity, noise, power consumption, voltage operation, speed imaging and dynamic range. In this paper, CMOS Image Sensors are reviewed, providing information on the latest advances achieved, their applications, the new challenges and their limitations. In conclusion, the State-of-the-art of CMOS Image Sensors. q

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Section: High Dynamic Range (Dr)mentioning

confidence: 99%

Review of CMOS image sensors

Bigas

Cabruja

Salví

2006

Microelectronics Journal

487

230

View full text Add to dashboard Cite

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“…With techniques like on-chip supply-boosting [7], current mode APS [8] and logarithmic APS [10], the power consumption of image sensors have been effectively reduced. But in order to ensure enough signal swing, the supply voltage (Vdd) of these analog pixels cannot be scaled too much [9].…”

Section: Introductionmentioning

confidence: 99%

A 21.4 pW/frame-pixel PWM image sensor with sub-threshold leakage reduction and two-step readout

Chen

Dan

Ding

et al. 2015

IEICE Electron. Express

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In this work we present a sub-1V pulse-width-modulation (PWM) CMOS image sensor. Ultra-low power consumption is achieved through the sub-threshold pixel bias, time-to-digital conversion and the array-level asynchronous counter. The 2-step readout scheme is adopted to improve the frame rate up to 68 fps. The prototype chip with 64 × 64 array has been fabricated in a 0.18 µm 1P6M CMOS process. Minimum functional analog supply of 0.36 V can be achieved, and the whole chip consumes only 1.14 µW at 13 fps, or 21.4 pW/frame-pixel. The dynamic range and FPN are measured to be 70 dB and 0.49% respectively.

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“…(2)(3)(4) The logarithmic APS has an advantage compared with the charge-accumulation-type APS. It has a wide dynamic range because of its image compression capability.…”

Section: Introductionmentioning

confidence: 99%

Low-Noise Logarithmic Active Pixel Sensor Using a Gate/N-Well-Tied PMOSFET-Type Photodetector

2009

Sensors and Materials

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A logarithmic active pixel sensor (APS) was designed as an image sensor. In the image sensor, a simplified correlated-double-sampling (SCDS) technique was applied to effectively reduce fixed pattern noise (FPN). In addition, a gate/n-well-tied p-channel metal-oxide-semiconductor (MOS)-type photodetector (PMOSPD) was used to obtain a large output swing. The measurement of the image sensor for image acquisition was carried out using a data acquisition (DAQ) card and LabVIEW system. From the experimental results, it was confirmed that the operation of the image sensor with noise reduction circuit is effective for reducing FPN.

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A logarithmic response CMOS image sensor with on-chip calibration

Cited by 186 publications

References 3 publications

Review of CMOS image sensors

Review of CMOS image sensors

A 21.4 pW/frame-pixel PWM image sensor with sub-threshold leakage reduction and two-step readout

Low-Noise Logarithmic Active Pixel Sensor Using a Gate/N-Well-Tied PMOSFET-Type Photodetector

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