A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

Si, Xin; Tu, Yung-Ning; Huang, Wei-Hsing; Su, Jian‐Wei; Lu, Pei-Jung; Wang, Jinghong; Liu, Chun‐Jen; Wu, Shaoen; Liu, Ruhui; Chou, Yen-Chi; Chung, Yen-Lin; Shih, William M.; Lo, Chung-Chuan; Liu, Ren-Shuo; Hsieh, Chih-Cheng; Tang, Kea-Tiong; Lien, Nan-Chun; Shih, Wei-Chiang; He, Yajuan; Li, Qiang; Chang, Meng‐Fan

doi:10.1109/jssc.2021.3073254

Cited by 73 publications

(8 citation statements)

References 25 publications

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“…The rapid growth of AI applications such as deep neural networks (DNNs) has made traditional accelerators based on the von Neumann architecture face increasingly prominent problems of high energy consumption and delays, which are mainly caused by the large amount of input, weights, and intermediate data that often move between the processor and memory [1,2,3,4,5,6,7,8,9,10,11]. This problem is known as the von Neumann bottleneck or "memory wall" [5,6,7,8,9,10]. IMC architecture is an effective approach to overcome this problem by effectively improving energy consumption and reducing latency by processing data in memory directly in parallel [6,9].…”

Section: Introductionmentioning

confidence: 99%

“…This problem is known as the von Neumann bottleneck or "memory wall" [5,6,7,8,9,10]. IMC architecture is an effective approach to overcome this problem by effectively improving energy consumption and reducing latency by processing data in memory directly in parallel [6,9].…”

Section: Introductionmentioning

confidence: 99%

“…Many studies on IMC have been performed [13,14,15,16,17,18,19,20,21,22,23,24,25,26,27], and the majority of them require the use of combinational logic such as the near-memory NOR gate to achieve complex operations such as XOR/XNOR and addition [10,25,26,27]. The IMC architecture with non-volatile memory represented by MRAM will have a higher capacity because MRAM cells have a lower number of transistors compared to SRAM [9].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations

Jin

Yin

Chen

et al. 2023

IEICE Electron. Express

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Traditional von Neumann architecture bottlenecks such as the "memory wall" limit artificial intelligence (AI) development, and inmemory computing (IMC) as a new computing architecture can solve the above problems. Spin-orbit-torque-magnetic random access memory (SOT-MRAM) has very good advantages in IMC architecture because of its good compatibility with CMOS, high tunneling magnetoresistance (TMR) ratio, and high energy efficiency. In this paper, we propose a 6T-3M-based MRAM-IMC architecture with reconfigurable memory mode and logical operation mode. The functionality of the proposed architecture is validated using the 28 nm process design kit and the SOT-MTJ model.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations

Jin

Yin

Chen

et al. 2023

IEICE Electron. Express

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show abstract

“…SRAM is a kind of volatile memory, which has the advantages of fast access speed, low static power consumption, and high durability, and is a common memory for CIM. Currently, SRAM-CIM can be divided into AD-CIM [1][2] [3] [4], DD-CIM [5], and TD-CIM [6][7] [8] according to the calculation method.…”

Section: Introductionmentioning

confidence: 99%

DominoCIM: A 28nm 138.04TOPS/W Spike-Domain Computing-in-Memory 6T-SRAM Macro for AI and Embedded Applications

Zhang

et al. 2023

J. Phys.: Conf. Ser.

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The realization of computing in memory based on SRAM(SRAM-CIM) can be divided into three domains: analog domain (AD-CIM), time domain (TD-CIM), and digital domain (DD-CIM). However, there exist corresponding disadvantages to the above methods. For AD-CIM, the calculation accuracy is poor. Moreover, the output stability of TD-CIM is limited. With a large overhead area, the layout and wiring of DD-CIM are complicated. Aiming to solve the shortcomings, this paper proposes a spike-domain circuit based on a pulse edge counting scheme. The circuit uses digital logic to realize the MAC operation, which is less affected by power, voltage, and temperature (PVT) and performs higher calculation accuracy. The circuit is transmitted serially through the delay chain to achieve a smaller area overhead. At 28 nm, the circuit accomplishes energy efficiency (EF) with 138.04TOPS/W for 4-bit multiplication and addition (MAC) operations, enabling full precision output and 3.42 times less energy consumption per operation than the previous SRAM-CIM.

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“…The advantages of MAC operations in the analog domain include energy savings and easy implementation of multibit multiplication; however, several disadvantages are also evident. For example, in the voltage domain [6,7], data are usually represented by a set of voltage levels, and the MAC operation is implemented by summing the discharge voltages of the bit lines. However, the operating voltage can limit the total amount of charge that can be accumulated, making it difficult to achieve a full-precision calculation because of noise and process variations.…”

Section: Introductionmentioning

confidence: 99%

In‐memory multibit multiplication and accumulation based on an automatic pulse generation circuit

Bai,

Guo,

Liu

et al. 2023

Electronics Letters

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Computing‐in‐memory (CIM) is a promising technique for solving the ‘memory wall’ and ‘power consumption wall’ problems. However, calculations in the analog domain are limited in terms of accuracy and sensitivity to process, voltage, and temperature changes. In this study, the authors proposed a CIM multiply‐and‐accumulate (MAC) circuit in which the MAC result was reflected by the pulse edge and converted into the final digital output using a dual‐edge counter quantization circuit, thereby improving the accuracy of the MAC operation and reducing the difficulty of quantization. The performance of the proposed CIM circuit was evaluated using a 28‐nm process. It could achieve 4‐bit multiplication without errors, with an energy efficiency of 24.38 to 670.86 TOPS/W.

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A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

Cited by 73 publications

References 25 publications

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations

DominoCIM: A 28nm 138.04TOPS/W Spike-Domain Computing-in-Memory 6T-SRAM Macro for AI and Embedded Applications

In‐memory multibit multiplication and accumulation based on an automatic pulse generation circuit

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