A Linearity Improvement Front End with Subharmonic Current Commutating Passive Mixer for 2.4 GHz Direct Conversion Receiver in 0.13 μm CMOS Technology

Abstract

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

A Highly Flexible Passive/Active Discrete-Time Delta-Sigma Receiver

“…Occupying key positions in the integrator, which handles high swing signals across a wide LO frequency range, the LO switches (LOI_P, LOI_N, LOQ_P, LOQ_N in Figure 2) are implemented as NMOS ones with a gate AC coupling technique. Furthermore, to achieve high linearity, the bulk and the source of each switch are connected [9]. The DC biasing voltage for the gates of these switches is tunable off-chip from 0.55 V to 0.85 V to optimize the operating point.…”

Methods for Model Complexity Reduction for the Nonlinear Calibration of Amplifiers Using Volterra Kernels

“…Modern communication systems are increasingly relying on digital signal processing, and the availability of the signal in digital form allows calibration in the digital domain, enabling the so-called digitally assisted analog electronics [1,2], where digital calibration is used to improve the performance of analog blocks. For instance, power amplifiers [3][4][5][6], IQ mixers [7,8] and ADCs [9][10][11][12][13] can be digitally enhanced, correcting nonlinear errors, I/Q mismatches, channel mismatches, etc. In particular, calibration can be used to reduce the nonlinearity of system components, and even of the entire system [14][15][16][17], by correcting nonlinear errors and improve the dynamic range of the system.…”