A linear systolic array for LU decomposition

Casseau, Emmanuel; Degrugillier, Dominique

doi:10.1109/icvd.1994.282718

Cited by 7 publications

(7 citation statements)

References 5 publications

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“…As illustrated in Table 5, upto 60% reduction in energy dissipation was obtained over a state-of-art linear array architecture [2]. Eest is the estimated energy.…”

Section: Floating-point Lu Decompositionmentioning

confidence: 99%

Energy-Efficient Computations on FPGAs

Prasanna

2005

J Supercomput

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Recently, energy dissipation for computations on FPGAs has become an important performance metric. In this paper, we summarize our recent efforts in developing an algorithm-level design methodology for optimizing the energy performance of FPGA based implementations. For kernels, our design methodology consists of four steps: domain selection, domain-specific energy modeling, domain-space exploration and low-level simulation. To achieve system-level energy-efficiency, we outline a design methodology that integrates the kernellevel design methodology. Both the design methodologies can be used to achieve not only energy-efficiency but also latency, area, and power efficiency. We consider signal processing kernels as illustrative examples and demonstrate energy and time efficient algorithms and implementations for these on FPGAs. Example energy performance optimization through algorithmic optimizations include the 29-51% improvement in energy performance for a matrix multiplication kernel, 57-78% improvement for a FFT kernel and the 10-60% improvement for a floatingpoint LU decomposition kernel over state-of-the-art implementations. Similarly, an improvement of 41 to 46% in energy performance was achieved by the system-level design approach over a greedy approach for a MVDR adaptive beamforming application. Finally we briefly describe a high-level tool for obtaining parameterized and energy-efficient designs on FPGAs.

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“…As illustrated in Table 5, upto 60% reduction in energy dissipation was obtained over a state-of-art linear array architecture [2]. Eest is the estimated energy.…”

Section: Floating-point Lu Decompositionmentioning

confidence: 99%

Energy-Efficient Computations on FPGAs

Prasanna

2005

J Supercomput

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“…With this fixed I/O bandwidth regardless of problem size, we achieve an optimal latency of b 2 + b − 1 with leading coefficient of 1. The best latency of previously proposed designs [3] is 2b(b + 1). In Theorem 2, a new parallel design on FPGAs for block LU decomposition is proposed.…”

Section: Time and Energy Efficient Designs For Matrix Factorizationmentioning

confidence: 99%

Time and Energy Efficient Matrix Factorization Using FPGAs

Choi

Prasanna

2003

Field Programmable Logic and Application

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Abstract. In this paper, new algorithms and architectures for matrix factorization are presented. Two fully-parallel and block-based designs for LU decomposition on configurable devices are proposed. A linear array architecture is employed to minimize the usage of long interconnects, leading to lower energy dissipation. The designs are made scalable by using a fixed I/O bandwidth independent of the problem size. High level models for energy profiling are built and the energy performance of many possible designs is predicted. Through the analysis of design tradeoffs, the block size that minimizes the total energy dissipation is identified. A set of candidate designs was implemented on the Xilinx Virtex-II to verify the estimates. Also, the performance of our designs is compared with that of state-of-the-art DSP based designs and with the performance of designs obtained using a state-of-the-art commercial compilation tool such as Celoxica DK1. Our designs on the FPGAs are significantly more time and energy efficient in both cases.

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“…Systolic arrays are very well suited to compute this kind of computation [17]. Applying the dependence method [18], a linear systolic array (Figure 8) has been specifically designed for the autocorrelation computation with 10 MAC-based cells as described in Figure 9.…”

Section: Hardware/software Implementationmentioning

confidence: 99%

Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications

Atri¹,

Sayadi²,

Elhamzi³

et al. 2012

JSIP

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The LPC "Linear Predictive Coding" algorithm is a widely used technique for voice coder. In this paper we present different implementations of the LPC algorithm used in the majority of voice decoding standard. The windowing/autocorrelation bloc is implemented by three different versions on an FPGA Spartan 3. Allowing the possibility to integrate a Microblaze processor core a first solution consists of a pure software implementation of the LPC using this core RISC processor. Second solution is a pure hardware architecture implemented using VHDL based methodology starting from description until integration. Finally, the autocorrelation core is then proposed to be implemented using hardware/software (HW/SW) architecture with the existing processor. Each architecture performances are compared for different data lengths.

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A linear systolic array for LU decomposition

Cited by 7 publications

References 5 publications

Energy-Efficient Computations on FPGAs

Energy-Efficient Computations on FPGAs

Time and Energy Efficient Matrix Factorization Using FPGAs

Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications

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