A Lightweight Method to Evaluate Effect of Approximate Memory with Hardware Performance Monitors

Abstract

Soramichi AKIYAMA †a) , Member SUMMARY The latency and the energy consumption of DRAM are serious concerns because (1) the latency has not improved much for decades and (2) recent machines have huge capacity of main memory. Device-level studies reduce them by shortening the wait time of DRAM internal operations so that they finish fast and consume less energy. Applying these techniques aggressively to achieve approximate memory is a promising direction to further reduce the overhead, given that many data-center applications today are to some extent robust to bit-flips. To advance research on approximate memory, it is required to evaluate its effect to applications so that both researchers and potential users of approximate memory can investigate how it affects realistic applications. However, hardware simulators are too slow to run workloads repeatedly with different parameters. To this end, we propose a lightweight method to evaluate effect of approximate memory. The idea is to count the number of DRAM internal operations that occur to approximate data of applications and calculate the probability of bit-flips based on it, instead of using heavy-weight simulators. The evaluation shows that our system is 3 orders of magnitude faster than cycle accurate simulators, and we also give case studies of evaluating effect of approximate memory to some realistic applications. key words: approximate memory, computer architecture, memory systems

Assessing Impact of Data Partitioning for Approximate Memory in C/C++ Code

“…For the former group, if one of the members other than the pointer is approximate data, they have approximate data and critical data interleaved because the pointer is most probably critical data. For example, our previous work [1] shows that mcf can yield the same result as the error-free one even when a member of arc_t is approximated. For the latter group, if the floating point number is approximate data (which is the case in many applications) and another member is critical data, they have approximate data and critical data interleaved.…”

“…CPUs [13]. Chang et al [5] measure the relationship between error rates and latency reduction for a large number of commercial DRAM chips, Das et al [9] and Zhang et al [32] prolong the interval of refreshing 1 for strong memory cells to reduce the average latency, and our previous work [1] estimates effect of approximate memory to realistic applications without simulation by counting the number of DRAM internal operations that induce errors.…”

The Granularity Gap Problem: A Hurdle for Applying Approximate Memory to Complex Data Layout

“…Approximate memory is especially beneficial for machine learning, multimedia, and graph processing applications, all of which incur many memory accesses and are tolerant to noisy data. For example, Stazi et al [28] show that allocating data in approximate memory for the x264 video encoder can yield acceptable results, and our previous work [1] show that a graph-based search algorithm (mcf in SPEC 2006) can yield the same result as error-free execution even when some bit-flips are injected. Regarding the performance improvement, Koppula et al [14] show 8% speedup in average for training various DNN models on approximate memory, and Lee et al [15] show that using Adaptive-Latency DRAM [16] for approximate memory gives 7% to 12% speedup in average for "32 benchmarks from Stream, SPEC CPU 2006, TPC and GUPS" (they do not show numbers for each benchmark though).…”

“…For step (1), there have been much effort [1,19,23] and it is out of the scope of this work, so we assume that discrimination of critical and non-critical data is given. For step (2), we must map the critical and non-critical data into different memory regions operated with different timing parameters.…”

“…performance of server-class CPUs plotted over time 1 . The figure shows an exponential growth of the single thread performance until recent years.…”