A Lightweight Memory Access Pattern Obfuscation Framework for NVM

Che, Yuezhi; Yang, Yuanzhou; Awad, Amro; Wang, Rujia

doi:10.1109/lca.2020.3041484

Cited by 6 publications

(3 citation statements)

References 11 publications

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“…In these methods, the wear-leveling algorithms usually keep track of the storage blocks and remap those blocks that are written heavily in a given time Article Title quanta to the lowest wear-out blocks. In storage class memory, wear leveling has almost the same objective, which is extending the lifetime of NVM devices by distributing the writes evenly across the memory blocks of NVM so that no hot area reaches its maximum lifespan by extremely high concentration of write operations [13,17,22,23,[37][38][39]. These methods usually are implemented in the memory controller level to protect NVMs.…”

Section: Wear Levelingmentioning

confidence: 99%

Challenges and future directions for Energy, Latency, and Lifetime Improvements in NVMs

Kargar

Nawab

2022

Preprint

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Recently, Non-Volatile Memory (NVM) technology has revolutionized the landscape of memory systems. With many advantages, such as non volatility and near zero standby power consumption, these byte-addressable memory technologies are taking the place of DRAMs. Nonetheless, they also present some limitations, such as limited write endurance, which hinders their widespread use in today’s systems. Furthermore, adjusting current data management systems to embrace these new memory technologies and all their potential is proving to be a nontrivial task. Because of this, a substantial amount of research has been done, from both the database community and the storage systems community, that tries to improve various aspects of NVMs to integrate these technologies into the memory hierarchy. In this tutorial we survey state-of-the-art work on deploying NVMs in database and storage systems communities and the ways their limitations are being handled within these communities. In particular, we focus on the challenges that are related to high energy consumption, low write endurance and extending the lifetime of NVM devices.

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Section: Wear Levelingmentioning

confidence: 99%

Challenges and future directions for Energy, Latency, and Lifetime Improvements in NVMs

Kargar

Nawab

2022

Preprint

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show abstract

“…In these methods, the wear-leveling algorithms usually keep track of the storage blocks and remap those blocks that are written heavily in a given time quanta to the lowest wear-out blocks. In storage class memory, wear leveling has almost the same objective, which is extending the lifetime of NVM devices by distributing the writes evenly across the memory blocks of NVM so that no hot area reaches its maximum lifespan by extremely high concentration of write operations [18,66,87,88,[100][101][102]. These methods usually are implemented in the memory controller level to protect NVMs.…”

Section: Wear Levelingmentioning

confidence: 99%

Challenges and future directions for energy, latency, and lifetime improvements in NVMs

Kargar

Nawab

2022

Distrib Parallel Databases

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Recently, non-volatile memory (NVM) technology has revolutionized the landscape of memory systems. With many advantages, such as non volatility and near zero standby power consumption, these byte-addressable memory technologies are taking the place of DRAMs. Nonetheless, they also present some limitations, such as limited write endurance, which hinders their widespread use in today’s systems. Furthermore, adjusting current data management systems to embrace these new memory technologies and all their potential is proving to be a nontrivial task. Because of this, a substantial amount of research has been done, from both the database community and the storage systems community, that tries to improve various aspects of NVMs to integrate these technologies into the memory hierarchy. In this work, which is the extended version of Kargar and Nawab (Proc. VLDB Endowment 14(12):3194–3197, 2021), we explore state-of-the-art work on deploying NVMs in database and storage systems communities and the ways their limitations are being handled within these communities. In particular, we focus on (1) the challenges that are related to high energy consumption, low write endurance and asymmetric read/write costs and (2) how these challenges can be solved using hardware and software solutions, especially by reducing the number of bit flips in write operations. We believe that this area has not gained enough attention in the data management community and this tutorial will provide information on how to integrate recent advances from the NVM storage community into existing and future data management systems.

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“…Therefore, an NVM-based ORAM system could bring benefits from the two worlds. While some prior works start to address this issue [6,12,14,46], they either work on a different threat model [6], or emphasis on write access overhead [46], or provide a less secure solution [12,14]. None of the prior works consider the crash consistency problem of ORAM when it is being implemented on NVM.…”

Section: Introductionmentioning

confidence: 99%

Ps-Oram

Liu

Xiao

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

Self Cite

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Oblivious RAM (ORAM) is a provable secure primitive to prevent access pattern leakage on the memory bus. By randomly remapping the data blocks and accessing redundant blocks, ORAM prevents access pattern leakage through obfuscation. Byte-addressable non-volatile memory (NVM) is considered as the candidate for main memory due to its better scalability, competitive performance, and persistent data store. While there is much prior work focusing on improving ORAM's performance on the conventional DRAM-based memory system, when the memory technology shifts to use NVM, ensuring an efficient crash-consistent ORAM is needed for security, correctness, and performance. Directly using traditional software-based crash consistency support for ORAM system is not only expensive but also insecure.In this work, we study how to persist ORAM construction with an NVM-based memory system. To support crash consistency without damaging ORAM system security and compromising the performance, we propose PS-ORAM. PS-ORAM consists of a novel ORAM controller design and a set of ORAM access protocols that support crash consistency.

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A Lightweight Memory Access Pattern Obfuscation Framework for NVM

Cited by 6 publications

References 11 publications

Challenges and future directions for Energy, Latency, and Lifetime Improvements in NVMs

Challenges and future directions for Energy, Latency, and Lifetime Improvements in NVMs

Challenges and future directions for energy, latency, and lifetime improvements in NVMs

Ps-Oram

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